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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
include/llvm/CodeGen/GlobalISel/CSEInfo.h 164 class RegisterBank;
include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h 32 class RegisterBank;
include/llvm/CodeGen/MIRParser/MIParser.h 26 class RegisterBank;
References
gen/lib/Target/AArch64/AArch64GenRegisterBank.inc 26 static RegisterBank *RegBanks[];
117 RegisterBank CCRegBank(/* ID */ AArch64::CCRegBankID, /* Name */ "CC", /* Size */ 32, /* CoveredRegClasses */ CCRegBankCoverageData, /* NumRegClasses */ 108);
118 RegisterBank FPRRegBank(/* ID */ AArch64::FPRRegBankID, /* Name */ "FPR", /* Size */ 512, /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 108);
119 RegisterBank GPRRegBank(/* ID */ AArch64::GPRRegBankID, /* Name */ "GPR", /* Size */ 64, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 108);
122 RegisterBank *AArch64GenRegisterBankInfo::RegBanks[] = {
gen/lib/Target/AMDGPU/AMDGPUGenRegisterBank.inc 27 static RegisterBank *RegBanks[];
214 RegisterBank SCCRegBank(/* ID */ AMDGPU::SCCRegBankID, /* Name */ "SCC", /* Size */ 32, /* CoveredRegClasses */ SCCRegBankCoverageData, /* NumRegClasses */ 114);
215 RegisterBank SGPRRegBank(/* ID */ AMDGPU::SGPRRegBankID, /* Name */ "SGPR", /* Size */ 1024, /* CoveredRegClasses */ SGPRRegBankCoverageData, /* NumRegClasses */ 114);
216 RegisterBank VCCRegBank(/* ID */ AMDGPU::VCCRegBankID, /* Name */ "VCC", /* Size */ 64, /* CoveredRegClasses */ VCCRegBankCoverageData, /* NumRegClasses */ 114);
217 RegisterBank VGPRRegBank(/* ID */ AMDGPU::VGPRRegBankID, /* Name */ "VGPR", /* Size */ 1024, /* CoveredRegClasses */ VGPRRegBankCoverageData, /* NumRegClasses */ 114);
220 RegisterBank *AMDGPUGenRegisterBankInfo::RegBanks[] = {
gen/lib/Target/ARM/ARMGenRegisterBank.inc 25 static RegisterBank *RegBanks[];
94 RegisterBank FPRRegBank(/* ID */ ARM::FPRRegBankID, /* Name */ "FPRB", /* Size */ 128, /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 122);
95 RegisterBank GPRRegBank(/* ID */ ARM::GPRRegBankID, /* Name */ "GPRB", /* Size */ 32, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 122);
98 RegisterBank *ARMGenRegisterBankInfo::RegBanks[] = {
gen/lib/Target/Mips/MipsGenRegisterBank.inc 25 static RegisterBank *RegBanks[];
83 RegisterBank FPRBRegBank(/* ID */ Mips::FPRBRegBankID, /* Name */ "FPRB", /* Size */ 128, /* CoveredRegClasses */ FPRBRegBankCoverageData, /* NumRegClasses */ 70);
84 RegisterBank GPRBRegBank(/* ID */ Mips::GPRBRegBankID, /* Name */ "GPRB", /* Size */ 32, /* CoveredRegClasses */ GPRBRegBankCoverageData, /* NumRegClasses */ 70);
87 RegisterBank *MipsGenRegisterBankInfo::RegBanks[] = {
gen/lib/Target/RISCV/RISCVGenRegisterBank.inc 24 static RegisterBank *RegBanks[];
48 RegisterBank GPRRegBank(/* ID */ RISCV::GPRRegBankID, /* Name */ "GPRB", /* Size */ 32, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 12);
51 RegisterBank *RISCVGenRegisterBankInfo::RegBanks[] = {
gen/lib/Target/X86/X86GenRegisterBank.inc 25 static RegisterBank *RegBanks[];
137 RegisterBank GPRRegBank(/* ID */ X86::GPRRegBankID, /* Name */ "GPR", /* Size */ 64, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 118);
138 RegisterBank VECRRegBank(/* ID */ X86::VECRRegBankID, /* Name */ "VECR", /* Size */ 512, /* CoveredRegClasses */ VECRRegBankCoverageData, /* NumRegClasses */ 118);
141 RegisterBank *X86GenRegisterBankInfo::RegBanks[] = {
include/llvm/CodeGen/GlobalISel/CSEInfo.h 181 const GISelInstProfileBuilder &addNodeIDRegType(const RegisterBank *RB) const;
include/llvm/CodeGen/GlobalISel/RegisterBank.h 74 bool operator==(const RegisterBank &OtherRB) const;
75 bool operator!=(const RegisterBank &OtherRB) const {
92 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h 59 const RegisterBank *RegBank;
65 const RegisterBank &RegBank)
386 RegisterBank **RegBanks;
417 RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks);
430 RegisterBank &getRegBank(unsigned ID) {
462 const RegisterBank &RegBank) const;
470 const RegisterBank &RegBank) const;
543 const RegisterBank *
574 const RegisterBank &getRegBank(unsigned ID) const {
583 const RegisterBank *getRegBank(Register Reg, const MachineRegisterInfo &MRI,
601 virtual const RegisterBank &
612 virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
612 virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
622 bool cannotCopy(const RegisterBank &Dst, const RegisterBank &Src,
622 bool cannotCopy(const RegisterBank &Dst, const RegisterBank &Src,
632 const RegisterBank *CurBank = nullptr) const {
include/llvm/CodeGen/MIRParser/MIParser.h 41 const RegisterBank *RegBank;
48 using Name2RegBankMap = StringMap<const RegisterBank *>;
146 const RegisterBank *getRegBank(StringRef Name);
include/llvm/CodeGen/MachineRegisterInfo.h 47 PointerUnion<const TargetRegisterClass *, const RegisterBank *>;
657 const RegisterBank *getRegBankOrNull(unsigned Reg) const {
659 return Val.dyn_cast<const RegisterBank *>();
673 void setRegBank(unsigned Reg, const RegisterBank &RegBank);
include/llvm/Support/PointerLikeTypeTraits.h 56 static inline void *getAsVoidPointer(T *P) { return P; }
57 static inline T *getFromVoidPointer(void *P) { return static_cast<T *>(P); }
59 enum { NumLowBitsAvailable = detail::ConstantLog2<alignof(T)>::value };
91 typedef PointerLikeTypeTraits<T *> NonConst;
93 static inline const void *getAsVoidPointer(const T *P) {
96 static inline const T *getFromVoidPointer(const void *P) {
lib/CodeGen/GlobalISel/CSEInfo.cpp 297 GISelInstProfileBuilder::addNodeIDRegType(const RegisterBank *RB) const {
lib/CodeGen/GlobalISel/RegBankSelect.cpp 120 const RegisterBank *CurRegBank = RBI->getRegBank(Reg, *MRI, *TRI);
121 const RegisterBank *DesiredRegBrank = ValMapping.BreakDown[0].RegBank;
243 const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI);
262 const RegisterBank *DesiredRegBrank = ValMapping.BreakDown[0].RegBank;
lib/CodeGen/GlobalISel/RegisterBank.cpp 71 bool RegisterBank::operator==(const RegisterBank &OtherRB) const {
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp 58 RegisterBankInfo::RegisterBankInfo(RegisterBank **RegBanks,
72 const RegisterBank &RegBank = getRegBank(Idx);
82 const RegisterBank *
90 if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>())
109 const RegisterBank *RegisterBankInfo::getRegBankFromConstraints(
119 const RegisterBank &RegBank = getRegBankFromRegClass(*RC);
134 const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
134 const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
190 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI);
194 const RegisterBank *CurRegBank = IsCopyLike ? AltRegBank : nullptr;
235 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI);
262 const RegisterBank *RegBank) {
275 const RegisterBank &RegBank) const {
292 const RegisterBank &RegBank) const {
lib/CodeGen/MIRParser/MIParser.cpp 297 const auto &RegBank = RBI->getRegBank(I);
311 const RegisterBank *PerTargetMIParsingState::getRegBank(StringRef Name) {
1260 const RegisterBank *RegBank = nullptr;
lib/CodeGen/MIRParser/MIRParser.cpp 520 const RegisterBank *RegBank = Target->getRegBank(VReg.Class.Value);
lib/CodeGen/MachineRegisterInfo.cpp 64 const RegisterBank &RegBank) {
lib/CodeGen/MachineVerifier.cpp 1731 const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
lib/Target/AArch64/AArch64GenRegisterBankInfo.def 122 const RegisterBank &RB) {
lib/Target/AArch64/AArch64InstructionSelector.cpp 111 const RegisterBank &RB,
151 const RegisterBank &DstRB, LLT ScalarTy,
304 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB,
335 getMinClassForRegBank(const RegisterBank &RB, unsigned SizeInBits,
412 const RegisterBank *PrevOpBank = nullptr;
429 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI);
555 static bool isValidCopy(const MachineInstr &I, const RegisterBank &DstBank,
622 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
623 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
648 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
649 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
983 const RegisterBank &RB = *RBI.getRegBank(LHS, MRI, TRI);
1346 const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
1346 const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
1497 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
1595 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
1596 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
1746 const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI);
1755 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI);
1828 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
1872 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
1949 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
1950 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
2017 const RegisterBank &RBDst = *RBI.getRegBank(DstReg, MRI, TRI);
2024 const RegisterBank &RBSrc = *RBI.getRegBank(SrcReg, MRI, TRI);
2283 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
2651 const RegisterBank &VecRB = *RBI.getRegBank(SrcReg, MRI, TRI);
2715 const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI);
2805 Optional<Register> DstReg, const RegisterBank &DstRB, LLT ScalarTy,
2823 const RegisterBank &VecRB = *RBI.getRegBank(VecReg, MRI, TRI);
2894 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
2921 const RegisterBank &DstRB =
3112 getInsertVecEltOpInfo(const RegisterBank &RB, unsigned EltSize) {
3301 const RegisterBank &FPRBank = *RBI.getRegBank(Op1, MRI, TRI);
3599 const RegisterBank *ScalarRB = RBI.getRegBank(ScalarReg, MRI, TRI);
3744 unsigned LaneIdx, const RegisterBank &RB,
3799 const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI);
3859 const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI);
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 51 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
56 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
61 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID);
204 unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A,
205 const RegisterBank &B,
225 const RegisterBank &AArch64RegisterBankInfo::getRegBankFromRegClass(
573 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI);
574 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI);
598 const RegisterBank &DstRB =
600 const RegisterBank &SrcRB =
lib/Target/AArch64/AArch64RegisterBankInfo.h 64 unsigned ValLength, const RegisterBank &RB);
132 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
132 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
135 const RegisterBank &
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 90 const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
90 const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
108 const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
108 const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
197 const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
197 const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
269 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);
305 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);
471 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI);
513 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI);
579 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI);
585 const RegisterBank *Src0Bank = RBI.getRegBank(Src0Reg, *MRI, TRI);
586 const RegisterBank *Src1Bank = RBI.getRegBank(Src1Reg, *MRI, TRI);
1173 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);
1174 const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI);
1232 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI);
1413 const RegisterBank *RB = MRI->getRegBankOrNull(I.getOperand(0).getReg());
1497 const RegisterBank *OpBank = RBI.getRegBank(GEPOp.getReg(), MRI, TRI);
1602 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);
1621 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);
1622 const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI);
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 44 const RegisterBank *NewBank;
48 ApplyRegBankMapping(MachineRegisterInfo &MRI_, const RegisterBank *RB)
66 const RegisterBank *RB = NewBank;
101 const RegisterBank &RBSGPR = getRegBank(AMDGPU::SGPRRegBankID);
105 const RegisterBank &RBVGPR = getRegBank(AMDGPU::VGPRRegBankID);
111 unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst,
112 const RegisterBank &Src,
144 const RegisterBank *CurBank) const {
167 const RegisterBank &AMDGPURegisterBankInfo::getRegBankFromRegClass(
611 const RegisterBank *Bank = getRegBank(Reg, *MRI, *TRI);
688 const RegisterBank *DefBank = getRegBank(Def.getReg(), MRI, *TRI);
967 const RegisterBank *OpBank = getRegBank(Reg, MRI, *TRI);
1002 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI);
1054 const RegisterBank *PtrBank = getRegBank(PtrReg, MRI, *TRI);
1442 const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI);
1463 const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI);
1500 const RegisterBank *SrcBank = getRegBank(SrcReg, MRI, *TRI);
1540 const RegisterBank *DstBank = SrcBank == &AMDGPU::SCCRegBank ?
1602 const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI);
1612 const RegisterBank *BankLo = getRegBank(Lo, MRI, *TRI);
1613 const RegisterBank *BankHi = getRegBank(Hi, MRI, *TRI);
1694 const RegisterBank *SrcBank = getRegBank(SrcReg, MRI, *TRI);
1759 const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI);
1760 const RegisterBank *SrcBank = getRegBank(SrcReg, MRI, *TRI);
1761 const RegisterBank *InsSrcBank = getRegBank(InsReg, MRI, *TRI);
1910 if (const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI)) {
2046 const RegisterBank *PtrBank = getRegBank(PtrReg, MRI, *TRI);
2076 const RegisterBank *Bank = getRegBank(Reg, MRI, TRI);
2148 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI);
2199 const RegisterBank *DstBank
2432 const RegisterBank *SrcBank = getRegBank(Src, MRI, *TRI);
lib/Target/AMDGPU/AMDGPURegisterBankInfo.h 146 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
146 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
150 const RegisterBank *CurBank = nullptr) const override;
152 const RegisterBank &
lib/Target/AMDGPU/SIRegisterInfo.cpp 1777 const RegisterBank &RB,
1837 if (const RegisterBank *RB = RCOrRB.dyn_cast<const RegisterBank*>())
1837 if (const RegisterBank *RB = RCOrRB.dyn_cast<const RegisterBank*>())
lib/Target/AMDGPU/SIRegisterInfo.h 251 const RegisterBank &Bank,
256 const RegisterBank &Bank,
lib/Target/ARM/ARMInstructionSelector.cpp 188 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI);
917 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
918 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1012 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
1013 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
lib/Target/ARM/ARMRegisterBankInfo.cpp 144 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);
175 const RegisterBank &ARMRegisterBankInfo::getRegBankFromRegClass(
lib/Target/ARM/ARMRegisterBankInfo.h 35 const RegisterBank &
lib/Target/Mips/MipsInstructionSelector.cpp 46 getRegClassForTypeOnBank(unsigned OpSize, const RegisterBank &RB,
93 const RegisterBank *RegBank = RBI.getRegBank(DstReg, MRI, TRI);
114 unsigned OpSize, const RegisterBank &RB,
lib/Target/Mips/MipsRegisterBankInfo.cpp 79 const RegisterBank &MipsRegisterBankInfo::getRegBankFromRegClass(
344 const RegisterBank *Bank =
lib/Target/Mips/MipsRegisterBankInfo.h 35 const RegisterBank &
lib/Target/X86/X86InstructionSelector.cpp 72 unsigned getLoadStoreOp(const LLT &Ty, const RegisterBank &RB, unsigned Opc,
126 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
168 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const {
198 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI);
234 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
238 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
394 const RegisterBank &RB,
508 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
717 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
718 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
806 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
807 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
892 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
893 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
1367 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1436 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1534 const RegisterBank *RegRB = RBI.getRegBank(DstReg, MRI, TRI);
lib/Target/X86/X86RegisterBankInfo.cpp 32 const RegisterBank &RBGPR = getRegBank(X86::GPRRegBankID);
43 const RegisterBank &X86RegisterBankInfo::getRegBankFromRegClass(
lib/Target/X86/X86RegisterBankInfo.h 67 const RegisterBank &
usr/include/c++/7.4.0/bits/move.h 72 constexpr _Tp&&
83 constexpr _Tp&&
usr/include/c++/7.4.0/bits/unique_ptr.h 824 make_unique(_Args&&... __args)