reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc

 2293   extern const TargetRegisterClass IntRegsRegClass;

References

gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc

 2584   &Hexagon::IntRegsRegClass,
 2589   &Hexagon::IntRegsRegClass,
 2952     &Hexagon::IntRegsRegClass,

lib/Target/Hexagon/HexagonAsmPrinter.cpp

   68   assert(Hexagon::IntRegsRegClass.contains(Reg));

lib/Target/Hexagon/HexagonBitSimplify.cpp

  913       return &Hexagon::IntRegsRegClass;
 1413   if (RC == &Hexagon::IntRegsRegClass) {
 2057       NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
 2063       NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
 2097   Register NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
 2154     Register NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
 2355     } else if (TC == &Hexagon::IntRegsRegClass) {
 2403   if (FRC != &Hexagon::IntRegsRegClass && FRC != &Hexagon::DoubleRegsRegClass)
 2585   if (FRC != &Hexagon::IntRegsRegClass && FRC != &Hexagon::DoubleRegsRegClass)
 3285         unsigned TfrI = (RC == &Hexagon::IntRegsRegClass) ? Hexagon::A2_tfrsi

lib/Target/Hexagon/HexagonBitTracker.cpp

  146       return Hexagon::IntRegsRegClass;
 1251   assert(PReg == 0 || Is64 || IntRegsRegClass.contains(PReg));

lib/Target/Hexagon/HexagonConstExtenders.cpp

 1528   llvm::Register DefR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);

lib/Target/Hexagon/HexagonConstPropagation.cpp

 2353   if (Hexagon::IntRegsRegClass.hasSubClassEq(RC))
 2893         NewRC = &Hexagon::IntRegsRegClass;

lib/Target/Hexagon/HexagonCopyToCombine.cpp

  138     return Hexagon::IntRegsRegClass.contains(DestReg) &&
  139            Hexagon::IntRegsRegClass.contains(SrcReg);
  158     return Hexagon::IntRegsRegClass.contains(DestReg) &&
  230   if (Hexagon::IntRegsRegClass.contains(Reg))
  449         } else if (Hexagon::IntRegsRegClass.contains(Reg))
  452         for (unsigned Reg : Hexagon::IntRegsRegClass)
  589   if (Hexagon::IntRegsRegClass.contains(LoRegDef)) {

lib/Target/Hexagon/HexagonExpandCondsets.cpp

 1097   if (RC == &Hexagon::IntRegsRegClass) {

lib/Target/Hexagon/HexagonFrameLowering.cpp

 1579   Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
 1604   Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
 1635   Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
 1670   Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
 1705   Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
 1956     SpillRCs.insert(&Hexagon::IntRegsRegClass);
 1964       unsigned Num = RC == &Hexagon::IntRegsRegClass ? NumberScavengerSlots : 1;

lib/Target/Hexagon/HexagonGenInsert.cpp

  641   return RC == &Hexagon::IntRegsRegClass || RC == &Hexagon::DoubleRegsRegClass;
 1414     bool R32 = MRI->getRegClass(NewR) == &Hexagon::IntRegsRegClass;

lib/Target/Hexagon/HexagonHardwareLoops.cpp

  899   const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass;
 1247     Register CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
 1260       Register CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);

lib/Target/Hexagon/HexagonISelLowering.cpp

 1269   addRegisterClass(MVT::i32,   &Hexagon::IntRegsRegClass);
 1270   addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
 1271   addRegisterClass(MVT::v4i8,  &Hexagon::IntRegsRegClass);
 1277   addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
 3009         return {0u, &Hexagon::IntRegsRegClass};

lib/Target/Hexagon/HexagonInstrInfo.cpp

  794   if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
  811       Hexagon::IntRegsRegClass.contains(SrcReg)) {
  816   if (Hexagon::IntRegsRegClass.contains(DestReg) &&
  823       Hexagon::IntRegsRegClass.contains(SrcReg)) {
  829       Hexagon::IntRegsRegClass.contains(DestReg)) {
  834   if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
  841       Hexagon::IntRegsRegClass.contains(DestReg)) {
  900   if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
  965   if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
 1989     TRC = &Hexagon::IntRegsRegClass;
 3742       if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
 3796         Hexagon::IntRegsRegClass.contains(SrcReg) &&
 3815     if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
 3832         (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
 3856     if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
 3898         Hexagon::IntRegsRegClass.contains(Src1Reg) &&
 3947       if (Hexagon::IntRegsRegClass.contains(SrcReg) &&

lib/Target/Hexagon/HexagonNewValueJump.cpp

  156     if (!Hexagon::IntRegsRegClass.contains(Op.getReg()))

lib/Target/Hexagon/HexagonRegisterInfo.cpp

  220     Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
  340   return &Hexagon::IntRegsRegClass;

lib/Target/Hexagon/HexagonSplitDouble.cpp

  815     const TargetRegisterClass *IntRC = &IntRegsRegClass;
  924   const TargetRegisterClass *IntRC = &IntRegsRegClass;
 1129   const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass;

lib/Target/Hexagon/HexagonVExtract.cpp

   70   Register ElemR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
   89   Register IdxR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
  147       Register BaseR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);