reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc

 2304   extern const TargetRegisterClass DoubleRegsRegClass;

References

gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc

 2616   &Hexagon::DoubleRegsRegClass,
 2621   &Hexagon::DoubleRegsRegClass,
 2963     &Hexagon::DoubleRegsRegClass,

lib/Target/Hexagon/HexagonAsmPrinter.cpp

   71   assert(Hexagon::DoubleRegsRegClass.contains(Pair));
  135       if (Hexagon::DoubleRegsRegClass.contains(RegNumber))

lib/Target/Hexagon/HexagonBitSimplify.cpp

 1419   if (RC == &Hexagon::DoubleRegsRegClass) {
 1566     if (MRI.getRegClass(R) != &Hexagon::DoubleRegsRegClass)
 1618       if (FRC == &Hexagon::DoubleRegsRegClass ||
 2025   Register NewR = MRI.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
 2298       NewR = MRI.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
 2348     if (TC == &Hexagon::DoubleRegsRegClass) {
 2403   if (FRC != &Hexagon::IntRegsRegClass && FRC != &Hexagon::DoubleRegsRegClass)
 2585   if (FRC != &Hexagon::IntRegsRegClass && FRC != &Hexagon::DoubleRegsRegClass)

lib/Target/Hexagon/HexagonBitTracker.cpp

 1250   bool Is64 = DoubleRegsRegClass.contains(PReg);

lib/Target/Hexagon/HexagonConstPropagation.cpp

 2201   if (RC != &Hexagon::DoubleRegsRegClass)
 2355   if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC))
 2895         NewRC = &Hexagon::DoubleRegsRegClass;

lib/Target/Hexagon/HexagonCopyToCombine.cpp

  446         if (Hexagon::DoubleRegsRegClass.contains(Reg)) {
  590     SuperRC = &Hexagon::DoubleRegsRegClass;
  869   if (Hexagon::DoubleRegsRegClass.contains(DoubleDestReg)) {

lib/Target/Hexagon/HexagonExpandCondsets.cpp

 1101   if (RC == &Hexagon::DoubleRegsRegClass) {

lib/Target/Hexagon/HexagonFrameLowering.cpp

 2435     if (!Hexagon::DoubleRegsRegClass.contains(R))

lib/Target/Hexagon/HexagonGenInsert.cpp

  641   return RC == &Hexagon::IntRegsRegClass || RC == &Hexagon::DoubleRegsRegClass;
  693   if (DstRC == &Hexagon::DoubleRegsRegClass)
 1420     if (R32 && MRI->getRegClass(IF.InsR) == &Hexagon::DoubleRegsRegClass) {

lib/Target/Hexagon/HexagonGenMux.cpp

  124       return Hexagon::DoubleRegsRegClass.contains(Reg);

lib/Target/Hexagon/HexagonHardwareLoops.cpp

  897   if (!SR && RC == &Hexagon::DoubleRegsRegClass)

lib/Target/Hexagon/HexagonISelLowering.cpp

 1272   addRegisterClass(MVT::i64,   &Hexagon::DoubleRegsRegClass);
 1273   addRegisterClass(MVT::v8i8,  &Hexagon::DoubleRegsRegClass);
 1274   addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
 1275   addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
 1278   addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
 3012         return {0u, &Hexagon::DoubleRegsRegClass};

lib/Target/Hexagon/HexagonInstrInfo.cpp

  799   if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
  904   } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
  968   } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
 1991     TRC = &Hexagon::DoubleRegsRegClass;

lib/Target/Hexagon/HexagonSplitDouble.cpp

  130     &Hexagon::DoubleRegsRegClass;

lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

  659   if (PacketRC == &Hexagon::DoubleRegsRegClass)