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| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Machine Code Emitter *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
uint64_t AVRMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
static const uint64_t InstBits[] = {
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(0),
UINT64_C(7168), // ADCRdRr
UINT64_C(3072), // ADDRdRr
UINT64_C(38400), // ADIWRdK
UINT64_C(28672), // ANDIRdK
UINT64_C(8192), // ANDRdRr
UINT64_C(37893), // ASRRd
UINT64_C(38024), // BCLRs
UINT64_C(63488), // BLD
UINT64_C(62464), // BRBCsk
UINT64_C(61440), // BRBSsk
UINT64_C(38296), // BREAK
UINT64_C(61441), // BREQk
UINT64_C(62468), // BRGEk
UINT64_C(61440), // BRLOk
UINT64_C(61444), // BRLTk
UINT64_C(61442), // BRMIk
UINT64_C(62465), // BRNEk
UINT64_C(62466), // BRPLk
UINT64_C(62464), // BRSHk
UINT64_C(37896), // BSETs
UINT64_C(64000), // BST
UINT64_C(2483945472), // CALLk
UINT64_C(38912), // CBIAb
UINT64_C(37888), // COMRd
UINT64_C(1024), // CPCRdRr
UINT64_C(12288), // CPIRdK
UINT64_C(5120), // CPRdRr
UINT64_C(4096), // CPSE
UINT64_C(37898), // DECRd
UINT64_C(37899), // DESK
UINT64_C(38169), // EICALL
UINT64_C(37913), // EIJMP
UINT64_C(38360), // ELPM
UINT64_C(36870), // ELPMRdZ
UINT64_C(36871), // ELPMRdZPi
UINT64_C(9216), // EORRdRr
UINT64_C(776), // FMUL
UINT64_C(896), // FMULS
UINT64_C(904), // FMULSU
UINT64_C(38153), // ICALL
UINT64_C(37897), // IJMP
UINT64_C(37891), // INCRd
UINT64_C(45056), // INRdA
UINT64_C(2483814400), // JMPk
UINT64_C(37382), // LACZRd
UINT64_C(37381), // LASZRd
UINT64_C(37383), // LATZRd
UINT64_C(32768), // LDDRdPtrQ
UINT64_C(57344), // LDIRdK
UINT64_C(32768), // LDRdPtr
UINT64_C(32770), // LDRdPtrPd
UINT64_C(32769), // LDRdPtrPi
UINT64_C(2415919104), // LDSRdK
UINT64_C(38344), // LPM
UINT64_C(36868), // LPMRdZ
UINT64_C(36869), // LPMRdZPi
UINT64_C(37894), // LSRRd
UINT64_C(11264), // MOVRdRr
UINT64_C(256), // MOVWRdRr
UINT64_C(39936), // MULRdRr
UINT64_C(512), // MULSRdRr
UINT64_C(768), // MULSURdRr
UINT64_C(37889), // NEGRd
UINT64_C(0), // NOP
UINT64_C(24576), // ORIRdK
UINT64_C(10240), // ORRdRr
UINT64_C(47104), // OUTARr
UINT64_C(36879), // POPRd
UINT64_C(37391), // PUSHRr
UINT64_C(53248), // RCALLk
UINT64_C(38152), // RET
UINT64_C(38168), // RETI
UINT64_C(49152), // RJMPk
UINT64_C(37895), // RORRd
UINT64_C(16384), // SBCIRdK
UINT64_C(2048), // SBCRdRr
UINT64_C(39424), // SBIAb
UINT64_C(39168), // SBICAb
UINT64_C(39680), // SBISAb
UINT64_C(38656), // SBIWRdK
UINT64_C(64512), // SBRCRrB
UINT64_C(65024), // SBRSRrB
UINT64_C(38280), // SLEEP
UINT64_C(38376), // SPM
UINT64_C(38392), // SPMZPi
UINT64_C(33280), // STDPtrQRr
UINT64_C(33282), // STPtrPdRr
UINT64_C(33281), // STPtrPiRr
UINT64_C(33280), // STPtrRr
UINT64_C(2449473536), // STSKRr
UINT64_C(20480), // SUBIRdK
UINT64_C(6144), // SUBRdRr
UINT64_C(37890), // SWAPRd
UINT64_C(38312), // WDR
UINT64_C(37380), // XCHZRd
UINT64_C(0)
};
const unsigned opcode = MI.getOpcode();
uint64_t Value = InstBits[opcode];
uint64_t op = 0;
(void)op; // suppress warning
switch (opcode) {
case AVR::BREAK:
case AVR::EICALL:
case AVR::EIJMP:
case AVR::ELPM:
case AVR::ICALL:
case AVR::IJMP:
case AVR::LPM:
case AVR::NOP:
case AVR::RET:
case AVR::RETI:
case AVR::SLEEP:
case AVR::SPM:
case AVR::SPMZPi:
case AVR::WDR: {
break;
}
case AVR::CBIAb:
case AVR::SBIAb:
case AVR::SBICAb:
case AVR::SBISAb: {
// op: A
op = encodeImm<AVR::fixup_port5, 0>(MI, 0, Fixups, STI);
op &= UINT64_C(31);
op <<= 3;
Value |= op;
// op: b
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
op &= UINT64_C(7);
Value |= op;
break;
}
case AVR::OUTARr: {
// op: A
op = encodeImm<AVR::fixup_port6, 0>(MI, 0, Fixups, STI);
Value |= (op & UINT64_C(48)) << 5;
Value |= (op & UINT64_C(15));
// op: r
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
op &= UINT64_C(31);
op <<= 4;
Value |= op;
break;
}
case AVR::MOVWRdRr: {
// op: d
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
op &= UINT64_C(30);
op <<= 3;
Value |= op;
// op: r
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
op &= UINT64_C(30);
op >>= 1;
Value |= op;
break;
}
case AVR::ASRRd:
case AVR::COMRd:
case AVR::DECRd:
case AVR::INCRd:
case AVR::LSRRd:
case AVR::NEGRd:
case AVR::POPRd:
case AVR::PUSHRr:
case AVR::RORRd:
case AVR::SWAPRd: {
// op: d
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
op &= UINT64_C(31);
op <<= 4;
Value |= op;
break;
}
case AVR::INRdA: {
// op: d
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
op &= UINT64_C(31);
op <<= 4;
Value |= op;
// op: A
op = encodeImm<AVR::fixup_port6, 0>(MI, 1, Fixups, STI);
Value |= (op & UINT64_C(48)) << 5;
Value |= (op & UINT64_C(15));
break;
}
case AVR::ADIWRdK:
case AVR::SBIWRdK: {
// op: dst
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
op &= UINT64_C(6);
op <<= 3;
Value |= op;
// op: k
op = encodeImm<AVR::fixup_6_adiw, 0>(MI, 2, Fixups, STI);
Value |= (op & UINT64_C(48)) << 2;
Value |= (op & UINT64_C(15));
break;
}
case AVR::CALLk:
case AVR::JMPk: {
// op: k
op = encodeCallTarget(MI, 0, Fixups, STI);
Value |= (op & UINT64_C(4063232)) << 3;
Value |= (op & UINT64_C(131071));
break;
}
case AVR::RCALLk:
case AVR::RJMPk: {
// op: k
op = encodeRelCondBrTarget<AVR::fixup_13_pcrel>(MI, 0, Fixups, STI);
op &= UINT64_C(4095);
Value |= op;
break;
}
case AVR::BREQk:
case AVR::BRGEk:
case AVR::BRLOk:
case AVR::BRLTk:
case AVR::BRMIk:
case AVR::BRNEk:
case AVR::BRPLk:
case AVR::BRSHk: {
// op: k
op = encodeRelCondBrTarget<AVR::fixup_7_pcrel>(MI, 0, Fixups, STI);
op &= UINT64_C(127);
op <<= 3;
Value |= op;
break;
}
case AVR::BRBCsk:
case AVR::BRBSsk: {
// op: k
op = encodeRelCondBrTarget<AVR::fixup_7_pcrel>(MI, 1, Fixups, STI);
op &= UINT64_C(127);
op <<= 3;
Value |= op;
// op: s
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
op &= UINT64_C(7);
Value |= op;
break;
}
case AVR::DESK: {
// op: k
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
op &= UINT64_C(15);
op <<= 4;
Value |= op;
break;
}
case AVR::STDPtrQRr: {
// op: memri
op = encodeMemri(MI, 0, Fixups, STI);
Value |= (op & UINT64_C(32)) << 8;
Value |= (op & UINT64_C(24)) << 7;
Value |= (op & UINT64_C(64)) >> 3;
Value |= (op & UINT64_C(7));
// op: reg
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
op &= UINT64_C(31);
op <<= 4;
Value |= op;
break;
}
case AVR::LDDRdPtrQ: {
// op: memri
op = encodeMemri(MI, 1, Fixups, STI);
Value |= (op & UINT64_C(32)) << 8;
Value |= (op & UINT64_C(24)) << 7;
Value |= (op & UINT64_C(64)) >> 3;
Value |= (op & UINT64_C(7));
// op: reg
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
op &= UINT64_C(31);
op <<= 4;
Value |= op;
break;
}
case AVR::STPtrRr: {
// op: ptrreg
op = encodeLDSTPtrReg(MI, 0, Fixups, STI);
op &= UINT64_C(3);
op <<= 2;
Value |= op;
// op: reg
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
op &= UINT64_C(31);
op <<= 4;
Value |= op;
Value = loadStorePostEncoder(MI, Value, STI);
break;
}
case AVR::LDRdPtr: {
// op: ptrreg
op = encodeLDSTPtrReg(MI, 1, Fixups, STI);
op &= UINT64_C(3);
op <<= 2;
Value |= op;
// op: reg
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
op &= UINT64_C(31);
op <<= 4;
Value |= op;
Value = loadStorePostEncoder(MI, Value, STI);
break;
}
case AVR::STPtrPdRr:
case AVR::STPtrPiRr: {
// op: ptrreg
op = encodeLDSTPtrReg(MI, 1, Fixups, STI);
op &= UINT64_C(3);
op <<= 2;
Value |= op;
// op: reg
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
op &= UINT64_C(31);
op <<= 4;
Value |= op;
Value = loadStorePostEncoder(MI, Value, STI);
break;
}
case AVR::LDRdPtrPd:
case AVR::LDRdPtrPi: {
// op: ptrreg
op = encodeLDSTPtrReg(MI, 2, Fixups, STI);
op &= UINT64_C(3);
op <<= 2;
Value |= op;
// op: reg
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
op &= UINT64_C(31);
op <<= 4;
Value |= op;
Value = loadStorePostEncoder(MI, Value, STI);
break;
}
case AVR::CPIRdK:
case AVR::LDIRdK: {
// op: rd
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
op &= UINT64_C(15);
op <<= 4;
Value |= op;
// op: k
op = encodeImm<AVR::fixup_ldi, 0>(MI, 1, Fixups, STI);
Value |= (op & UINT64_C(240)) << 4;
Value |= (op & UINT64_C(15));
break;
}
case AVR::ANDIRdK:
case AVR::ORIRdK:
case AVR::SBCIRdK:
case AVR::SUBIRdK: {
// op: rd
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
op &= UINT64_C(15);
op <<= 4;
Value |= op;
// op: k
op = encodeImm<AVR::fixup_ldi, 0>(MI, 2, Fixups, STI);
Value |= (op & UINT64_C(240)) << 4;
Value |= (op & UINT64_C(15));
break;
}
case AVR::MULSRdRr:
case AVR::MULSURdRr: {
// op: rd
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
op &= UINT64_C(15);
op <<= 4;
Value |= op;
// op: rr
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
op &= UINT64_C(15);
Value |= op;
break;
}
case AVR::LDSRdK: {
// op: rd
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
op &= UINT64_C(31);
op <<= 20;
Value |= op;
// op: k
op = encodeImm<AVR::fixup_16, 2>(MI, 1, Fixups, STI);
op &= UINT64_C(65535);
Value |= op;
break;
}
case AVR::LACZRd:
case AVR::LASZRd:
case AVR::LATZRd:
case AVR::XCHZRd: {
// op: rd
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
op &= UINT64_C(31);
op <<= 4;
Value |= op;
break;
}
case AVR::BLD:
case AVR::BST:
case AVR::SBRCRrB:
case AVR::SBRSRrB: {
// op: rd
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
op &= UINT64_C(31);
op <<= 4;
Value |= op;
// op: b
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
op &= UINT64_C(7);
Value |= op;
break;
}
case AVR::CPCRdRr:
case AVR::CPRdRr:
case AVR::CPSE:
case AVR::MOVRdRr:
case AVR::MULRdRr: {
// op: rd
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
op &= UINT64_C(31);
op <<= 4;
Value |= op;
// op: rr
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
Value |= (op & UINT64_C(16)) << 5;
Value |= (op & UINT64_C(15));
break;
}
case AVR::ADCRdRr:
case AVR::ADDRdRr:
case AVR::ANDRdRr:
case AVR::EORRdRr:
case AVR::ORRdRr:
case AVR::SBCRdRr:
case AVR::SUBRdRr: {
// op: rd
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
op &= UINT64_C(31);
op <<= 4;
Value |= op;
// op: rr
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
Value |= (op & UINT64_C(16)) << 5;
Value |= (op & UINT64_C(15));
break;
}
case AVR::FMUL:
case AVR::FMULS:
case AVR::FMULSU: {
// op: rd
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
op &= UINT64_C(7);
op <<= 4;
Value |= op;
// op: rr
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
op &= UINT64_C(7);
Value |= op;
break;
}
case AVR::STSKRr: {
// op: rd
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
op &= UINT64_C(31);
op <<= 20;
Value |= op;
// op: k
op = encodeImm<AVR::fixup_16, 2>(MI, 0, Fixups, STI);
op &= UINT64_C(65535);
Value |= op;
break;
}
case AVR::ELPMRdZ:
case AVR::ELPMRdZPi:
case AVR::LPMRdZ:
case AVR::LPMRdZPi: {
// op: reg
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
op &= UINT64_C(31);
op <<= 4;
Value |= op;
break;
}
case AVR::BCLRs:
case AVR::BSETs: {
// op: s
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
op &= UINT64_C(7);
op <<= 4;
Value |= op;
break;
}
default:
std::string msg;
raw_string_ostream Msg(msg);
Msg << "Not supported instr: " << MI;
report_fatal_error(Msg.str());
}
return Value;
}
#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
#undef ENABLE_INSTR_PREDICATE_VERIFIER
#include <sstream>
// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
Feature_HasSRAMBit = 13,
Feature_HasJMPCALLBit = 7,
Feature_HasIJMPCALLBit = 6,
Feature_HasEIJMPCALLBit = 3,
Feature_HasADDSUBIWBit = 0,
Feature_HasSmallStackBit = 14,
Feature_HasMOVWBit = 10,
Feature_HasLPMBit = 8,
Feature_HasLPMXBit = 9,
Feature_HasELPMBit = 4,
Feature_HasELPMXBit = 5,
Feature_HasSPMBit = 11,
Feature_HasSPMXBit = 12,
Feature_HasDESBit = 2,
Feature_SupportsRMWBit = 17,
Feature_SupportsMultiplicationBit = 16,
Feature_HasBREAKBit = 1,
Feature_HasTinyEncodingBit = 15,
};
#ifndef NDEBUG
static const char *SubtargetFeatureNames[] = {
"Feature_HasADDSUBIW",
"Feature_HasBREAK",
"Feature_HasDES",
"Feature_HasEIJMPCALL",
"Feature_HasELPM",
"Feature_HasELPMX",
"Feature_HasIJMPCALL",
"Feature_HasJMPCALL",
"Feature_HasLPM",
"Feature_HasLPMX",
"Feature_HasMOVW",
"Feature_HasSPM",
"Feature_HasSPMX",
"Feature_HasSRAM",
"Feature_HasSmallStack",
"Feature_HasTinyEncoding",
"Feature_SupportsMultiplication",
"Feature_SupportsRMW",
nullptr
};
#endif // NDEBUG
FeatureBitset AVRMCCodeEmitter::
computeAvailableFeatures(const FeatureBitset& FB) const {
FeatureBitset Features;
if ((FB[AVR::FeatureSRAM]))
Features.set(Feature_HasSRAMBit);
if ((FB[AVR::FeatureJMPCALL]))
Features.set(Feature_HasJMPCALLBit);
if ((FB[AVR::FeatureIJMPCALL]))
Features.set(Feature_HasIJMPCALLBit);
if ((FB[AVR::FeatureEIJMPCALL]))
Features.set(Feature_HasEIJMPCALLBit);
if ((FB[AVR::FeatureADDSUBIW]))
Features.set(Feature_HasADDSUBIWBit);
if ((FB[AVR::FeatureSmallStack]))
Features.set(Feature_HasSmallStackBit);
if ((FB[AVR::FeatureMOVW]))
Features.set(Feature_HasMOVWBit);
if ((FB[AVR::FeatureLPM]))
Features.set(Feature_HasLPMBit);
if ((FB[AVR::FeatureLPMX]))
Features.set(Feature_HasLPMXBit);
if ((FB[AVR::FeatureELPM]))
Features.set(Feature_HasELPMBit);
if ((FB[AVR::FeatureELPMX]))
Features.set(Feature_HasELPMXBit);
if ((FB[AVR::FeatureSPM]))
Features.set(Feature_HasSPMBit);
if ((FB[AVR::FeatureSPMX]))
Features.set(Feature_HasSPMXBit);
if ((FB[AVR::FeatureDES]))
Features.set(Feature_HasDESBit);
if ((FB[AVR::FeatureRMW]))
Features.set(Feature_SupportsRMWBit);
if ((FB[AVR::FeatureMultiplication]))
Features.set(Feature_SupportsMultiplicationBit);
if ((FB[AVR::FeatureBREAK]))
Features.set(Feature_HasBREAKBit);
if ((FB[AVR::FeatureTinyEncoding]))
Features.set(Feature_HasTinyEncodingBit);
return Features;
}
#ifndef NDEBUG
// Feature bitsets.
enum : uint8_t {
CEFBS_None,
CEFBS_HasADDSUBIW,
CEFBS_HasBREAK,
CEFBS_HasDES,
CEFBS_HasEIJMPCALL,
CEFBS_HasELPM,
CEFBS_HasELPMX,
CEFBS_HasIJMPCALL,
CEFBS_HasJMPCALL,
CEFBS_HasLPM,
CEFBS_HasLPMX,
CEFBS_HasMOVW,
CEFBS_HasSPM,
CEFBS_HasSPMX,
CEFBS_HasSRAM,
CEFBS_SupportsMultiplication,
CEFBS_SupportsRMW,
};
static constexpr FeatureBitset FeatureBitsets[] = {
{}, // CEFBS_None
{Feature_HasADDSUBIWBit, },
{Feature_HasBREAKBit, },
{Feature_HasDESBit, },
{Feature_HasEIJMPCALLBit, },
{Feature_HasELPMBit, },
{Feature_HasELPMXBit, },
{Feature_HasIJMPCALLBit, },
{Feature_HasJMPCALLBit, },
{Feature_HasLPMBit, },
{Feature_HasLPMXBit, },
{Feature_HasMOVWBit, },
{Feature_HasSPMBit, },
{Feature_HasSPMXBit, },
{Feature_HasSRAMBit, },
{Feature_SupportsMultiplicationBit, },
{Feature_SupportsRMWBit, },
};
#endif // NDEBUG
void AVRMCCodeEmitter::verifyInstructionPredicates(
const MCInst &Inst, const FeatureBitset &AvailableFeatures) const {
#ifndef NDEBUG
static uint8_t RequiredFeaturesRefs[] = {
CEFBS_None, // PHI = 0
CEFBS_None, // INLINEASM = 1
CEFBS_None, // INLINEASM_BR = 2
CEFBS_None, // CFI_INSTRUCTION = 3
CEFBS_None, // EH_LABEL = 4
CEFBS_None, // GC_LABEL = 5
CEFBS_None, // ANNOTATION_LABEL = 6
CEFBS_None, // KILL = 7
CEFBS_None, // EXTRACT_SUBREG = 8
CEFBS_None, // INSERT_SUBREG = 9
CEFBS_None, // IMPLICIT_DEF = 10
CEFBS_None, // SUBREG_TO_REG = 11
CEFBS_None, // COPY_TO_REGCLASS = 12
CEFBS_None, // DBG_VALUE = 13
CEFBS_None, // DBG_LABEL = 14
CEFBS_None, // REG_SEQUENCE = 15
CEFBS_None, // COPY = 16
CEFBS_None, // BUNDLE = 17
CEFBS_None, // LIFETIME_START = 18
CEFBS_None, // LIFETIME_END = 19
CEFBS_None, // STACKMAP = 20
CEFBS_None, // FENTRY_CALL = 21
CEFBS_None, // PATCHPOINT = 22
CEFBS_None, // LOAD_STACK_GUARD = 23
CEFBS_None, // STATEPOINT = 24
CEFBS_None, // LOCAL_ESCAPE = 25
CEFBS_None, // FAULTING_OP = 26
CEFBS_None, // PATCHABLE_OP = 27
CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 28
CEFBS_None, // PATCHABLE_RET = 29
CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 30
CEFBS_None, // PATCHABLE_TAIL_CALL = 31
CEFBS_None, // PATCHABLE_EVENT_CALL = 32
CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 33
CEFBS_None, // ICALL_BRANCH_FUNNEL = 34
CEFBS_None, // G_ADD = 35
CEFBS_None, // G_SUB = 36
CEFBS_None, // G_MUL = 37
CEFBS_None, // G_SDIV = 38
CEFBS_None, // G_UDIV = 39
CEFBS_None, // G_SREM = 40
CEFBS_None, // G_UREM = 41
CEFBS_None, // G_AND = 42
CEFBS_None, // G_OR = 43
CEFBS_None, // G_XOR = 44
CEFBS_None, // G_IMPLICIT_DEF = 45
CEFBS_None, // G_PHI = 46
CEFBS_None, // G_FRAME_INDEX = 47
CEFBS_None, // G_GLOBAL_VALUE = 48
CEFBS_None, // G_EXTRACT = 49
CEFBS_None, // G_UNMERGE_VALUES = 50
CEFBS_None, // G_INSERT = 51
CEFBS_None, // G_MERGE_VALUES = 52
CEFBS_None, // G_BUILD_VECTOR = 53
CEFBS_None, // G_BUILD_VECTOR_TRUNC = 54
CEFBS_None, // G_CONCAT_VECTORS = 55
CEFBS_None, // G_PTRTOINT = 56
CEFBS_None, // G_INTTOPTR = 57
CEFBS_None, // G_BITCAST = 58
CEFBS_None, // G_INTRINSIC_TRUNC = 59
CEFBS_None, // G_INTRINSIC_ROUND = 60
CEFBS_None, // G_LOAD = 61
CEFBS_None, // G_SEXTLOAD = 62
CEFBS_None, // G_ZEXTLOAD = 63
CEFBS_None, // G_INDEXED_LOAD = 64
CEFBS_None, // G_INDEXED_SEXTLOAD = 65
CEFBS_None, // G_INDEXED_ZEXTLOAD = 66
CEFBS_None, // G_STORE = 67
CEFBS_None, // G_INDEXED_STORE = 68
CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 69
CEFBS_None, // G_ATOMIC_CMPXCHG = 70
CEFBS_None, // G_ATOMICRMW_XCHG = 71
CEFBS_None, // G_ATOMICRMW_ADD = 72
CEFBS_None, // G_ATOMICRMW_SUB = 73
CEFBS_None, // G_ATOMICRMW_AND = 74
CEFBS_None, // G_ATOMICRMW_NAND = 75
CEFBS_None, // G_ATOMICRMW_OR = 76
CEFBS_None, // G_ATOMICRMW_XOR = 77
CEFBS_None, // G_ATOMICRMW_MAX = 78
CEFBS_None, // G_ATOMICRMW_MIN = 79
CEFBS_None, // G_ATOMICRMW_UMAX = 80
CEFBS_None, // G_ATOMICRMW_UMIN = 81
CEFBS_None, // G_ATOMICRMW_FADD = 82
CEFBS_None, // G_ATOMICRMW_FSUB = 83
CEFBS_None, // G_FENCE = 84
CEFBS_None, // G_BRCOND = 85
CEFBS_None, // G_BRINDIRECT = 86
CEFBS_None, // G_INTRINSIC = 87
CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 88
CEFBS_None, // G_ANYEXT = 89
CEFBS_None, // G_TRUNC = 90
CEFBS_None, // G_CONSTANT = 91
CEFBS_None, // G_FCONSTANT = 92
CEFBS_None, // G_VASTART = 93
CEFBS_None, // G_VAARG = 94
CEFBS_None, // G_SEXT = 95
CEFBS_None, // G_SEXT_INREG = 96
CEFBS_None, // G_ZEXT = 97
CEFBS_None, // G_SHL = 98
CEFBS_None, // G_LSHR = 99
CEFBS_None, // G_ASHR = 100
CEFBS_None, // G_ICMP = 101
CEFBS_None, // G_FCMP = 102
CEFBS_None, // G_SELECT = 103
CEFBS_None, // G_UADDO = 104
CEFBS_None, // G_UADDE = 105
CEFBS_None, // G_USUBO = 106
CEFBS_None, // G_USUBE = 107
CEFBS_None, // G_SADDO = 108
CEFBS_None, // G_SADDE = 109
CEFBS_None, // G_SSUBO = 110
CEFBS_None, // G_SSUBE = 111
CEFBS_None, // G_UMULO = 112
CEFBS_None, // G_SMULO = 113
CEFBS_None, // G_UMULH = 114
CEFBS_None, // G_SMULH = 115
CEFBS_None, // G_FADD = 116
CEFBS_None, // G_FSUB = 117
CEFBS_None, // G_FMUL = 118
CEFBS_None, // G_FMA = 119
CEFBS_None, // G_FMAD = 120
CEFBS_None, // G_FDIV = 121
CEFBS_None, // G_FREM = 122
CEFBS_None, // G_FPOW = 123
CEFBS_None, // G_FEXP = 124
CEFBS_None, // G_FEXP2 = 125
CEFBS_None, // G_FLOG = 126
CEFBS_None, // G_FLOG2 = 127
CEFBS_None, // G_FLOG10 = 128
CEFBS_None, // G_FNEG = 129
CEFBS_None, // G_FPEXT = 130
CEFBS_None, // G_FPTRUNC = 131
CEFBS_None, // G_FPTOSI = 132
CEFBS_None, // G_FPTOUI = 133
CEFBS_None, // G_SITOFP = 134
CEFBS_None, // G_UITOFP = 135
CEFBS_None, // G_FABS = 136
CEFBS_None, // G_FCOPYSIGN = 137
CEFBS_None, // G_FCANONICALIZE = 138
CEFBS_None, // G_FMINNUM = 139
CEFBS_None, // G_FMAXNUM = 140
CEFBS_None, // G_FMINNUM_IEEE = 141
CEFBS_None, // G_FMAXNUM_IEEE = 142
CEFBS_None, // G_FMINIMUM = 143
CEFBS_None, // G_FMAXIMUM = 144
CEFBS_None, // G_GEP = 145
CEFBS_None, // G_PTR_MASK = 146
CEFBS_None, // G_SMIN = 147
CEFBS_None, // G_SMAX = 148
CEFBS_None, // G_UMIN = 149
CEFBS_None, // G_UMAX = 150
CEFBS_None, // G_BR = 151
CEFBS_None, // G_BRJT = 152
CEFBS_None, // G_INSERT_VECTOR_ELT = 153
CEFBS_None, // G_EXTRACT_VECTOR_ELT = 154
CEFBS_None, // G_SHUFFLE_VECTOR = 155
CEFBS_None, // G_CTTZ = 156
CEFBS_None, // G_CTTZ_ZERO_UNDEF = 157
CEFBS_None, // G_CTLZ = 158
CEFBS_None, // G_CTLZ_ZERO_UNDEF = 159
CEFBS_None, // G_CTPOP = 160
CEFBS_None, // G_BSWAP = 161
CEFBS_None, // G_BITREVERSE = 162
CEFBS_None, // G_FCEIL = 163
CEFBS_None, // G_FCOS = 164
CEFBS_None, // G_FSIN = 165
CEFBS_None, // G_FSQRT = 166
CEFBS_None, // G_FFLOOR = 167
CEFBS_None, // G_FRINT = 168
CEFBS_None, // G_FNEARBYINT = 169
CEFBS_None, // G_ADDRSPACE_CAST = 170
CEFBS_None, // G_BLOCK_ADDR = 171
CEFBS_None, // G_JUMP_TABLE = 172
CEFBS_None, // G_DYN_STACKALLOC = 173
CEFBS_None, // ADCWRdRr = 174
CEFBS_None, // ADDWRdRr = 175
CEFBS_None, // ADJCALLSTACKDOWN = 176
CEFBS_None, // ADJCALLSTACKUP = 177
CEFBS_None, // ANDIWRdK = 178
CEFBS_None, // ANDWRdRr = 179
CEFBS_None, // ASRWRd = 180
CEFBS_None, // Asr16 = 181
CEFBS_None, // Asr8 = 182
CEFBS_None, // AtomicFence = 183
CEFBS_None, // AtomicLoad16 = 184
CEFBS_None, // AtomicLoad8 = 185
CEFBS_None, // AtomicLoadAdd16 = 186
CEFBS_None, // AtomicLoadAdd8 = 187
CEFBS_None, // AtomicLoadAnd16 = 188
CEFBS_None, // AtomicLoadAnd8 = 189
CEFBS_None, // AtomicLoadOr16 = 190
CEFBS_None, // AtomicLoadOr8 = 191
CEFBS_None, // AtomicLoadSub16 = 192
CEFBS_None, // AtomicLoadSub8 = 193
CEFBS_None, // AtomicLoadXor16 = 194
CEFBS_None, // AtomicLoadXor8 = 195
CEFBS_None, // AtomicStore16 = 196
CEFBS_None, // AtomicStore8 = 197
CEFBS_None, // COMWRd = 198
CEFBS_None, // CPCWRdRr = 199
CEFBS_None, // CPWRdRr = 200
CEFBS_None, // EORWRdRr = 201
CEFBS_None, // FRMIDX = 202
CEFBS_None, // INWRdA = 203
CEFBS_HasSRAM, // LDDWRdPtrQ = 204
CEFBS_HasSRAM, // LDDWRdYQ = 205
CEFBS_None, // LDIWRdK = 206
CEFBS_HasSRAM, // LDSWRdK = 207
CEFBS_HasSRAM, // LDWRdPtr = 208
CEFBS_HasSRAM, // LDWRdPtrPd = 209
CEFBS_HasSRAM, // LDWRdPtrPi = 210
CEFBS_HasLPMX, // LPMWRdZ = 211
CEFBS_HasLPMX, // LPMWRdZPi = 212
CEFBS_None, // LSLWRd = 213
CEFBS_None, // LSRWRd = 214
CEFBS_None, // Lsl16 = 215
CEFBS_None, // Lsl8 = 216
CEFBS_None, // Lsr16 = 217
CEFBS_None, // Lsr8 = 218
CEFBS_None, // ORIWRdK = 219
CEFBS_None, // ORWRdRr = 220
CEFBS_None, // OUTWARr = 221
CEFBS_HasSRAM, // POPWRd = 222
CEFBS_HasSRAM, // PUSHWRr = 223
CEFBS_None, // ROLWRd = 224
CEFBS_None, // RORWRd = 225
CEFBS_None, // Rol16 = 226
CEFBS_None, // Rol8 = 227
CEFBS_None, // Ror16 = 228
CEFBS_None, // Ror8 = 229
CEFBS_None, // SBCIWRdK = 230
CEFBS_None, // SBCWRdRr = 231
CEFBS_None, // SEXT = 232
CEFBS_None, // SPREAD = 233
CEFBS_None, // SPWRITE = 234
CEFBS_None, // STDSPQRr = 235
CEFBS_HasSRAM, // STDWPtrQRr = 236
CEFBS_None, // STDWSPQRr = 237
CEFBS_HasSRAM, // STSWKRr = 238
CEFBS_HasSRAM, // STWPtrPdRr = 239
CEFBS_HasSRAM, // STWPtrPiRr = 240
CEFBS_HasSRAM, // STWPtrRr = 241
CEFBS_None, // SUBIWRdK = 242
CEFBS_None, // SUBWRdRr = 243
CEFBS_None, // Select16 = 244
CEFBS_None, // Select8 = 245
CEFBS_None, // ZEXT = 246
CEFBS_None, // ADCRdRr = 247
CEFBS_None, // ADDRdRr = 248
CEFBS_HasADDSUBIW, // ADIWRdK = 249
CEFBS_None, // ANDIRdK = 250
CEFBS_None, // ANDRdRr = 251
CEFBS_None, // ASRRd = 252
CEFBS_None, // BCLRs = 253
CEFBS_None, // BLD = 254
CEFBS_None, // BRBCsk = 255
CEFBS_None, // BRBSsk = 256
CEFBS_HasBREAK, // BREAK = 257
CEFBS_None, // BREQk = 258
CEFBS_None, // BRGEk = 259
CEFBS_None, // BRLOk = 260
CEFBS_None, // BRLTk = 261
CEFBS_None, // BRMIk = 262
CEFBS_None, // BRNEk = 263
CEFBS_None, // BRPLk = 264
CEFBS_None, // BRSHk = 265
CEFBS_None, // BSETs = 266
CEFBS_None, // BST = 267
CEFBS_HasJMPCALL, // CALLk = 268
CEFBS_None, // CBIAb = 269
CEFBS_None, // COMRd = 270
CEFBS_None, // CPCRdRr = 271
CEFBS_None, // CPIRdK = 272
CEFBS_None, // CPRdRr = 273
CEFBS_None, // CPSE = 274
CEFBS_None, // DECRd = 275
CEFBS_HasDES, // DESK = 276
CEFBS_HasEIJMPCALL, // EICALL = 277
CEFBS_HasEIJMPCALL, // EIJMP = 278
CEFBS_HasELPM, // ELPM = 279
CEFBS_HasELPMX, // ELPMRdZ = 280
CEFBS_HasELPMX, // ELPMRdZPi = 281
CEFBS_None, // EORRdRr = 282
CEFBS_SupportsMultiplication, // FMUL = 283
CEFBS_SupportsMultiplication, // FMULS = 284
CEFBS_SupportsMultiplication, // FMULSU = 285
CEFBS_HasIJMPCALL, // ICALL = 286
CEFBS_HasIJMPCALL, // IJMP = 287
CEFBS_None, // INCRd = 288
CEFBS_None, // INRdA = 289
CEFBS_HasJMPCALL, // JMPk = 290
CEFBS_SupportsRMW, // LACZRd = 291
CEFBS_SupportsRMW, // LASZRd = 292
CEFBS_SupportsRMW, // LATZRd = 293
CEFBS_HasSRAM, // LDDRdPtrQ = 294
CEFBS_None, // LDIRdK = 295
CEFBS_HasSRAM, // LDRdPtr = 296
CEFBS_HasSRAM, // LDRdPtrPd = 297
CEFBS_HasSRAM, // LDRdPtrPi = 298
CEFBS_HasSRAM, // LDSRdK = 299
CEFBS_HasLPM, // LPM = 300
CEFBS_HasLPMX, // LPMRdZ = 301
CEFBS_HasLPMX, // LPMRdZPi = 302
CEFBS_None, // LSRRd = 303
CEFBS_None, // MOVRdRr = 304
CEFBS_HasMOVW, // MOVWRdRr = 305
CEFBS_SupportsMultiplication, // MULRdRr = 306
CEFBS_SupportsMultiplication, // MULSRdRr = 307
CEFBS_SupportsMultiplication, // MULSURdRr = 308
CEFBS_None, // NEGRd = 309
CEFBS_None, // NOP = 310
CEFBS_None, // ORIRdK = 311
CEFBS_None, // ORRdRr = 312
CEFBS_None, // OUTARr = 313
CEFBS_HasSRAM, // POPRd = 314
CEFBS_HasSRAM, // PUSHRr = 315
CEFBS_None, // RCALLk = 316
CEFBS_None, // RET = 317
CEFBS_None, // RETI = 318
CEFBS_None, // RJMPk = 319
CEFBS_None, // RORRd = 320
CEFBS_None, // SBCIRdK = 321
CEFBS_None, // SBCRdRr = 322
CEFBS_None, // SBIAb = 323
CEFBS_None, // SBICAb = 324
CEFBS_None, // SBISAb = 325
CEFBS_HasADDSUBIW, // SBIWRdK = 326
CEFBS_None, // SBRCRrB = 327
CEFBS_None, // SBRSRrB = 328
CEFBS_None, // SLEEP = 329
CEFBS_HasSPM, // SPM = 330
CEFBS_HasSPMX, // SPMZPi = 331
CEFBS_HasSRAM, // STDPtrQRr = 332
CEFBS_HasSRAM, // STPtrPdRr = 333
CEFBS_HasSRAM, // STPtrPiRr = 334
CEFBS_HasSRAM, // STPtrRr = 335
CEFBS_HasSRAM, // STSKRr = 336
CEFBS_None, // SUBIRdK = 337
CEFBS_None, // SUBRdRr = 338
CEFBS_None, // SWAPRd = 339
CEFBS_None, // WDR = 340
CEFBS_SupportsRMW, // XCHZRd = 341
};
assert(Inst.getOpcode() < 342);
const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Inst.getOpcode()]];
FeatureBitset MissingFeatures =
(AvailableFeatures & RequiredFeatures) ^
RequiredFeatures;
if (MissingFeatures.any()) {
std::ostringstream Msg;
Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str()
<< " instruction but the ";
for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
if (MissingFeatures.test(i))
Msg << SubtargetFeatureNames[i] << " ";
Msg << "predicate(s) are not met";
report_fatal_error(Msg.str());
}
#else
// Silence unused variable warning on targets that don't use MCII for other purposes (e.g. BPF).
(void)MCII;
#endif // NDEBUG
}
#endif
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