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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc10729 { 641 /* lsl */, ARM::tLSLri, Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_31 }, },
10736 { 641 /* lsl */, ARM::tLSLri, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_31 }, },
gen/lib/Target/ARM/ARMGenDAGISel.inc27695 /* 59843*/ OPC_EmitNode1, TARGET_VAL(ARM::tLSLri), 0,
27717 /* 59913*/ OPC_EmitNode1, TARGET_VAL(ARM::tLSLri), 0,
27743 /* 59991*/ OPC_EmitNode1, TARGET_VAL(ARM::tLSLri), 0,
27765 /* 60061*/ OPC_EmitNode1, TARGET_VAL(ARM::tLSLri), 0,
35415 /* 78089*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::tLSLri), 0,
37632 /* 82911*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::tLSLri), 0,
gen/lib/Target/ARM/ARMGenFastISel.inc 6110 return fastEmitInst_ri(ARM::tLSLri, &ARM::tGPRRegClass, Op0, Op0IsKill, imm1);
gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc 6704 case ARM::tLSLri:
lib/Target/ARM/ARMAsmPrinter.cpp 1672 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri)
1728 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri)
lib/Target/ARM/ARMBaseInstrInfo.cpp 634 case ARM::tLSLri: // LSL (immediate) T1
2336 {ARM::tLSLSri, ARM::tLSLri},
2831 case ARM::tLSLri:
lib/Target/ARM/ARMConstantIslandPass.cpp 2227 if (Shift->getOpcode() != ARM::tLSLri ||
lib/Target/ARM/ARMFastISel.cpp 2698 unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
lib/Target/ARM/ARMFeatures.h 37 case ARM::tLSLri:
lib/Target/ARM/ARMISelDAGToDAG.cpp 2878 Opc = (Opc == ARM::tLSLri) ? ARM::t2LSLri : ARM::t2LSRri;
2893 NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first);
2902 NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first);
2909 NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first);
lib/Target/ARM/ARMISelLowering.cpp 9668 BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 9506 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
9594 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
10211 if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock())
lib/Target/ARM/Thumb1FrameLowering.cpp 422 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), ARM::R4)
lib/Target/ARM/Thumb2SizeReduction.cpp 100 { ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },