reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenAsmMatcher.inc

10608   { 544 /* ldr */, ARM::tLDRspi, Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbSPI }, },

gen/lib/Target/ARM/ARMGenDAGISel.inc

27212 /* 58732*/          OPC_MorphNodeTo1, TARGET_VAL(ARM::tLDRspi), 0|OPFL_Chain|OPFL_MemRefs,
27313 /* 58958*/          OPC_MorphNodeTo1, TARGET_VAL(ARM::tLDRspi), 0|OPFL_Chain|OPFL_MemRefs,
27324 /* 58983*/          OPC_MorphNodeTo1, TARGET_VAL(ARM::tLDRspi), 0|OPFL_Chain|OPFL_MemRefs,
27335 /* 59008*/          OPC_MorphNodeTo1, TARGET_VAL(ARM::tLDRspi), 0|OPFL_Chain|OPFL_MemRefs,

gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc

 7738     case ARM::tLDRspi:

lib/Target/ARM/ARMBaseInstrInfo.cpp

 1457   case ARM::tLDRspi:

lib/Target/ARM/ARMBaseRegisterInfo.cpp

  571   case ARM::tSTRspi: case ARM::tLDRspi:

lib/Target/ARM/ARMFeatures.h

   65   case ARM::tLDRspi:

lib/Target/ARM/ARMISelLowering.cpp

 9629     BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)

lib/Target/ARM/ARMLoadStoreOptimizer.cpp

  230       Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi)
  274   case ARM::tLDRspi:
  392   return Opc == ARM::tLDRi || Opc == ARM::tLDRspi;
  424   case ARM::tLDRspi:
  443   case ARM::tLDRspi:
  663   } else if (Offset != 0 || Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) {
 1576   case ARM::tLDRspi:

lib/Target/ARM/Thumb1FrameLowering.cpp

  456   if (MI.getOpcode() == ARM::tLDRspi && MI.getOperand(1).isFI() &&
  721     BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRspi))

lib/Target/ARM/Thumb1InstrInfo.cpp

  125     BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)

lib/Target/ARM/Thumb2SizeReduction.cpp

  131   { ARM::t2LDRi12,ARM::tLDRi,   ARM::tLDRspi,  5,   8,   1,   0,  0,0, 0,1,0 },

lib/Target/ARM/ThumbRegisterInfo.cpp

  349   case ARM::tLDRspi:
  417     if (Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) {
  515     if (Opcode == ARM::tLDRspi) {