|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc10226 { 14 /* add */, ARM::tADDrr, Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10247 { 14 /* add */, ARM::tADDrr, Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, },
gen/lib/Target/ARM/ARMGenDAGISel.inc 1074 /* 2251*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::tADDrr), 0,
1083 /* 2275*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::tADDrr), 0,
5803 /* 11876*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::tADDrr), 0,
gen/lib/Target/ARM/ARMGenFastISel.inc 3407 return fastEmitInst_rr(ARM::tADDrr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc 7162 case ARM::tADDrr:
lib/Target/ARM/ARMBaseInstrInfo.cpp 628 case ARM::tADDrr: // ADD (register) T1
2328 {ARM::tADDSrr, ARM::tADDrr},
2818 OI->getOpcode() == ARM::tADDrr) &&
2836 case ARM::tADDrr:
lib/Target/ARM/ARMConstantIslandPass.cpp 2261 if (Add->getOpcode() != ARM::tADDrr ||
lib/Target/ARM/ARMFeatures.h 31 case ARM::tADDrr:
lib/Target/ARM/ARMISelLowering.cpp 9680 BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
9699 BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
lib/Target/ARM/Thumb2SizeReduction.cpp 85 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
87 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
lib/Target/ARM/ThumbRegisterInfo.cpp 171 : ((isHigh || !CanChangeCC) ? ARM::tADDhirr : ARM::tADDrr);