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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc10232 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_T2SOImmNeg }, },
10233 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_T2SOImmNeg }, },
10246 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImmNeg }, },
10253 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, },
10254 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, },
10263 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, },
10264 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, },
11354 { 1600 /* sub */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, },
11369 { 1600 /* sub */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImm }, },
11378 { 1600 /* sub */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImm }, },
gen/lib/Target/ARM/ARMGenDAGISel.inc 5100 /* 10328*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::t2SUBri), 0,
5277 /* 10714*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::t2SUBri), 0,
33281 /* 73244*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::t2SUBri), 0,
gen/lib/Target/ARM/ARMGenFastISel.inc 6684 return fastEmitInst_ri(ARM::t2SUBri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
gen/lib/Target/ARM/ARMGenGlobalISel.inc 3593 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBri,
gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc16049 case ARM::t2SUBri: {
lib/Target/ARM/ARMAsmPrinter.cpp 1176 case ARM::t2SUBri:
lib/Target/ARM/ARMBaseInstrInfo.cpp 2342 {ARM::t2SUBSri, ARM::t2SUBri},
2791 (OI->getOpcode() == ARM::SUBri || OI->getOpcode() == ARM::t2SUBri) &&
2873 case ARM::t2SUBri:
3109 Opc == ARM::SUBri || Opc == ARM::t2SUBri ||
3289 NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2ADDri : ARM::t2SUBri;
3292 NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2SUBri : ARM::t2ADDri;
lib/Target/ARM/ARMFrameLowering.cpp 1208 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri;
lib/Target/ARM/ARMISelLowering.cpp10214 TII->get(IsThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 708 isThumb2 ? ARM::t2SUBri :
1188 case ARM::t2SUBri:
lib/Target/ARM/ARMLowOverheadLoops.cpp 396 TII->get(ARM::t2SUBri));
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 7714 case ARM::t2SUBri:
9767 Inst.setOpcode(ARM::t2SUBri);
9791 case ARM::t2SUBri: {
lib/Target/ARM/Disassembler/ARMDisassembler.cpp 598 case ARM::t2SUBri:
lib/Target/ARM/Thumb2InstrInfo.cpp 322 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
335 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
503 MI.setDesc(TII.get(ARM::t2SUBri));
lib/Target/ARM/Thumb2SizeReduction.cpp 118 { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0,0,0 },