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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
include/llvm/CodeGen/MachineFunction.h 646 unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC);
References
lib/CodeGen/CallingConvLower.cpp 253 unsigned VReg = MF.addLiveIn(PReg, RC);
lib/Target/AArch64/AArch64CallLowering.cpp 405 unsigned X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass);
lib/Target/AArch64/AArch64FastISel.cpp 3049 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
lib/Target/AArch64/AArch64ISelLowering.cpp 3228 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3339 unsigned X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass);
3423 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
3455 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
5589 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
lib/Target/AMDGPU/AMDGPUCallLowering.cpp 329 Register LiveInReturn = MF.addLiveIn(TRI->getReturnAddressReg(MF),
394 MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SGPR_128RegClass);
400 MF.addLiveIn(DispatchPtrReg, &AMDGPU::SGPR_64RegClass);
406 MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
423 MF.addLiveIn(DispatchIDReg, &AMDGPU::SGPR_64RegClass);
429 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass);
578 Register LiveInReturn = MF.addLiveIn(ReturnAddrReg,
586 MF.addLiveIn(ImplicitBufferPtrReg, &AMDGPU::SGPR_64RegClass);
lib/Target/AMDGPU/R600ISelLowering.cpp 1605 unsigned Reg = MF.addLiveIn(VA.getLocReg(), &R600::R600_Reg128RegClass);
lib/Target/AMDGPU/SIISelLowering.cpp 1622 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1630 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1638 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1669 Register LiveInVReg = MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
1687 MF.addLiveIn(Reg, RC);
1763 MF.addLiveIn(ImplicitBufferPtrReg, &AMDGPU::SGPR_64RegClass);
1770 MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SGPR_128RegClass);
1776 MF.addLiveIn(DispatchPtrReg, &AMDGPU::SGPR_64RegClass);
1782 MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
1791 Register VReg = MF.addLiveIn(InputPtrReg, &AMDGPU::SGPR_64RegClass);
1797 MF.addLiveIn(DispatchIDReg, &AMDGPU::SGPR_64RegClass);
1803 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass);
1819 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
1825 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
1831 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
1837 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
1858 MF.addLiveIn(PrivateSegmentWaveByteOffsetReg, &AMDGPU::SGPR_32RegClass);
2170 Reg = MF.addLiveIn(Reg, RC);
4553 unsigned Reg = MF.addLiveIn(TRI->getReturnAddressReg(MF), getRegClassFor(VT, Op.getNode()->isDivergent()));
lib/Target/ARM/ARMFastISel.cpp 3059 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
lib/Target/ARM/ARMISelLowering.cpp 3602 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3847 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3861 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
3917 unsigned VReg = MF.addLiveIn(Reg, RC);
4069 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
5546 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
lib/Target/AVR/AVRISelLowering.cpp 1080 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
lib/Target/Hexagon/HexagonISelLowering.cpp 987 unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
lib/Target/Lanai/LanaiISelLowering.cpp 1071 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
lib/Target/Mips/MipsFastISel.cpp 1468 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, Allocation[ArgNo].RC);
lib/Target/Mips/MipsISelLowering.cpp 2410 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
lib/Target/PowerPC/PPCISelLowering.cpp 3534 unsigned RegLo = MF.addLiveIn(VA.getLocReg(), RC);
3535 unsigned RegHi = MF.addLiveIn(ArgLocs[++i].getLocReg(), RC);
3543 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3636 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
3655 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
3840 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3875 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3899 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
3912 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3940 VReg = MF.addLiveIn(FPR[FPR_idx],
3945 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3958 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
4000 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
4030 unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
4085 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4251 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4253 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4274 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4276 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4299 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4317 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4347 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
4349 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
4367 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
4442 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4444 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
lib/Target/RISCV/RISCVISelLowering.cpp 717 Register Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(XLenVT));
lib/Target/Sparc/SparcISelLowering.cpp 434 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
600 unsigned VReg = MF.addLiveIn(VA.getLocReg(),
671 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
2673 unsigned RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT));
lib/Target/SystemZ/SystemZISelLowering.cpp 1421 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
3100 unsigned LinkReg = MF.addLiveIn(SystemZ::R14D, &SystemZ::GR64BitRegClass);
lib/Target/X86/X86FastISel.cpp 3141 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
lib/Target/X86/X86ISelLowering.cpp 2756 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2758 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
3271 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3373 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
3378 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
3381 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
3469 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);