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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h 644 constrainGenericRegister(Register Reg, const TargetRegisterClass &RC,
References
lib/CodeGen/GlobalISel/Utils.cpp 34 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI))
lib/Target/AArch64/AArch64InstructionSelector.cpp 607 RBI.constrainGenericRegister(I.getOperand(0).getReg(), *To, MRI);
746 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
1303 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI);
1306 RBI.constrainGenericRegister(DefReg, AArch64::GPR32RegClass, MRI);
1356 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI);
1558 if (!RBI.constrainGenericRegister(DefReg, FPRRC, MRI)) {
1632 RBI.constrainGenericRegister(I.getOperand(0).getReg(),
1667 RBI.constrainGenericRegister(I.getOperand(2).getReg(),
1815 return RBI.constrainGenericRegister(DstReg, AArch64::GPR64allRegClass,
1969 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
1970 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
2097 if (!RBI.constrainGenericRegister(SrcReg, AArch64::GPR32RegClass, MRI)) {
2286 RBI.constrainGenericRegister(DstReg, *DstRC, MRI);
2394 RBI.constrainGenericRegister(I.getOperand(0).getReg(), AArch64::GPR64RegClass,
2677 RBI.constrainGenericRegister(DstReg, *SrcRC, MRI);
2840 RBI.constrainGenericRegister(*DstReg, *DstRC, MRI);
2860 RBI.constrainGenericRegister(*DstReg, *DstRC, MRI);
3044 RBI.constrainGenericRegister(CopyTo, *RC, MRI);
3719 RBI.constrainGenericRegister(Copy.getReg(0), AArch64::FPR64RegClass, MRI);
3838 RBI.constrainGenericRegister(DstReg, *RC, MRI);
3912 RBI.constrainGenericRegister(DstReg, *RC, MRI);
3988 RBI.constrainGenericRegister(I.getOperand(2).getReg(),
4004 RBI.constrainGenericRegister(I.getOperand(0).getReg(),
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 128 return RBI.constrainGenericRegister(DstReg, *RC, *MRI);
133 if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI))
148 if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI))
160 if (SrcRC && !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))
175 RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI);
211 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI);
285 return RBI.constrainGenericRegister(DstReg, *RC, *MRI);
389 if (!RBI.constrainGenericRegister(DstReg, RC, *MRI))
428 if (!RBI.constrainGenericRegister(Dst0Reg, AMDGPU::SReg_32RegClass, MRI) ||
429 !RBI.constrainGenericRegister(Src0Reg, AMDGPU::SReg_32RegClass, MRI) ||
430 !RBI.constrainGenericRegister(Src1Reg, AMDGPU::SReg_32RegClass, MRI))
454 RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI);
488 if (SrcRC && !RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI))
492 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))
517 if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))
533 if (DstRC && !RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI))
552 (RC && RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI))) {
598 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) ||
599 !RBI.constrainGenericRegister(Src0Reg, *Src0RC, *MRI) ||
600 !RBI.constrainGenericRegister(Src1Reg, *Src1RC, *MRI))
737 RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32RegClass, *MRI);
750 RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(),
1200 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) ||
1201 !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) {
1256 return RBI.constrainGenericRegister(DstReg, *DstRC, *MRI);
1302 if (!RBI.constrainGenericRegister(SrcReg, AMDGPU::SReg_32RegClass, *MRI))
1311 return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, *MRI);
1334 return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_64RegClass, *MRI);
1349 return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, *MRI);
1467 return RBI.constrainGenericRegister(DstReg, *DstRC, *MRI);
1608 return RBI.constrainGenericRegister(
1635 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) ||
1636 !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 780 constrainGenericRegister(Op.getReg(), AMDGPU::VGPR_32RegClass, MRI);
1013 constrainGenericRegister(Reg, AMDGPU::VGPR_32RegClass, MRI);
lib/Target/ARM/ARMInstructionSelector.cpp 222 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
1163 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
lib/Target/Mips/MipsInstructionSelector.cpp 105 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
382 return RBI.constrainGenericRegister(DestReg, *DefRC, MRI);
lib/Target/X86/X86InstructionSelector.cpp 297 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
694 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
695 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
757 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
758 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
811 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
812 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
913 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
914 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
1028 RBI.constrainGenericRegister(
1108 if (!RBI.constrainGenericRegister(CarryInReg, X86::GR32RegClass, MRI))
1130 !RBI.constrainGenericRegister(CarryOutReg, X86::GR32RegClass, MRI))
1220 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
1221 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
1257 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
1258 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
1501 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
1634 if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) ||
1635 !RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) ||
1636 !RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) {