reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/MachineInstr.h

 1080     return getOpcode() == TargetOpcode::PHI ||
 1166     case TargetOpcode::PHI:

lib/CodeGen/DetectDeadLanes.cpp

  143   case TargetOpcode::PHI:
  238   case TargetOpcode::PHI:
  340   case TargetOpcode::PHI:

lib/CodeGen/MachineSSAUpdater.cpp

  189   MachineInstrBuilder InsertedPHI = InsertNewDef(TargetOpcode::PHI, BB,
  306     MachineInstr *PHI = InsertNewDef(TargetOpcode::PHI, BB, Loc,

lib/CodeGen/ModuloSchedule.cpp

  552                   TII->get(TargetOpcode::PHI), NewReg);
  668                     TII->get(TargetOpcode::PHI), NewReg);
 1437     BuildMI(*BB, MI, DebugLoc(), TII->get(TargetOpcode::PHI), R)
 1486   BuildMI(*BB, BB->getFirstNonPHI(), DebugLoc(), TII->get(TargetOpcode::PHI), R)
 1689     MachineInstr *NI = BuildMI(NewBB, DebugLoc(), TII->get(TargetOpcode::PHI), R)

lib/CodeGen/PeepholeOptimizer.cpp

  767                                     TII.get(TargetOpcode::PHI), NewVR);

lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

  287           BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);

lib/CodeGen/SwiftErrorValueTracking.cpp

  246                   TII->get(TargetOpcode::PHI), PHIVReg);

lib/Target/AArch64/AArch64InstructionSelector.cpp

 1332     if (Opcode == TargetOpcode::PHI || Opcode == TargetOpcode::G_PHI) {
 1354       I.setDesc(TII.get(TargetOpcode::PHI));

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

  210   I.setDesc(TII.get(TargetOpcode::PHI));

lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp

 1485         BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI),
 1530         BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI),
 1579         BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI),
 1770                                     TII->get(TargetOpcode::PHI), DestRegister);
 2161                                       TII->get(TargetOpcode::PHI), DestReg);
 2180                       TII->get(TargetOpcode::PHI), NewBackedgeReg);
 2455               TII->get(TargetOpcode::PHI), NewDestReg);

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

  732   B.buildInstr(TargetOpcode::PHI)

lib/Target/AMDGPU/SIISelLowering.cpp

 3189   BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiReg)
 3195   BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiExec)

lib/Target/AMDGPU/SIInstrInfo.cpp

 6105         BuildMI(*(MF), Branch->getDebugLoc(), get(TargetOpcode::PHI), DstReg);

lib/Target/ARM/ARMInstructionSelector.cpp

 1159     I.setDesc(TII.get(PHI));

lib/Target/Hexagon/HexagonBitSimplify.cpp

 3072   BuildMI(LB, At, At->getDebugLoc(), HII->get(TargetOpcode::PHI), PhiR)

lib/Target/Hexagon/HexagonHardwareLoops.cpp

 1902       const MCInstrDesc &PD = TII->get(TargetOpcode::PHI);

lib/Target/Hexagon/HexagonInstrInfo.cpp

 2338   case TargetOpcode::PHI:

lib/Target/Hexagon/HexagonNewValueJump.cpp

  221         MII->getOpcode() == TargetOpcode::PHI ||

lib/Target/Hexagon/HexagonSplitDouble.cpp

  173     case TargetOpcode::PHI:
  319     case TargetOpcode::PHI:
 1003     case TargetOpcode::PHI:

lib/Target/Mips/MipsInstructionSelector.cpp

  381     I.setDesc(TII.get(TargetOpcode::PHI));

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

  415   BuildMI(*DoneMBB, DoneMBB->begin(), DL, TII.get(TargetOpcode::PHI), OutReg)

lib/Target/X86/X86DomainReassignment.cpp

  608   Converters[{MaskDomain, TargetOpcode::PHI}] =
  609       new InstrIgnore(TargetOpcode::PHI);