|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenCallingConv.inc 45 if (LocVT == MVT::iPTR) {
50 if (LocVT == MVT::v2f32) {
55 if (LocVT == MVT::v2f64 ||
56 LocVT == MVT::v4f32) {
62 if (LocVT == MVT::v2i32 ||
63 LocVT == MVT::v2f32 ||
64 LocVT == MVT::v4i16 ||
65 LocVT == MVT::v4f16 ||
66 LocVT == MVT::v8i8) {
73 if (LocVT == MVT::v2i64 ||
74 LocVT == MVT::v2f64 ||
75 LocVT == MVT::v4i32 ||
76 LocVT == MVT::v4f32 ||
77 LocVT == MVT::v8i16 ||
78 LocVT == MVT::v8f16 ||
79 LocVT == MVT::v16i8) {
86 if (LocVT == MVT::i64) {
88 if (LocVT == MVT::i64) {
105 if (LocVT == MVT::i64) {
126 if (LocVT == MVT::i64) {
135 if (LocVT == MVT::i64) {
148 if (LocVT == MVT::nxv16i8 ||
149 LocVT == MVT::nxv8i16 ||
150 LocVT == MVT::nxv4i32 ||
151 LocVT == MVT::nxv2i64 ||
152 LocVT == MVT::nxv2f16 ||
153 LocVT == MVT::nxv4f16 ||
154 LocVT == MVT::nxv8f16 ||
155 LocVT == MVT::nxv1f32 ||
156 LocVT == MVT::nxv2f32 ||
157 LocVT == MVT::nxv4f32 ||
158 LocVT == MVT::nxv1f64 ||
159 LocVT == MVT::nxv2f64) {
169 if (LocVT == MVT::nxv16i8 ||
170 LocVT == MVT::nxv8i16 ||
171 LocVT == MVT::nxv4i32 ||
172 LocVT == MVT::nxv2i64 ||
173 LocVT == MVT::nxv2f16 ||
174 LocVT == MVT::nxv4f16 ||
175 LocVT == MVT::nxv8f16 ||
176 LocVT == MVT::nxv1f32 ||
177 LocVT == MVT::nxv2f32 ||
178 LocVT == MVT::nxv4f32 ||
179 LocVT == MVT::nxv1f64 ||
180 LocVT == MVT::nxv2f64) {
185 if (LocVT == MVT::nxv2i1 ||
186 LocVT == MVT::nxv4i1 ||
187 LocVT == MVT::nxv8i1 ||
188 LocVT == MVT::nxv16i1) {
198 if (LocVT == MVT::nxv2i1 ||
199 LocVT == MVT::nxv4i1 ||
200 LocVT == MVT::nxv8i1 ||
201 LocVT == MVT::nxv16i1) {
206 if (LocVT == MVT::i1 ||
207 LocVT == MVT::i8 ||
208 LocVT == MVT::i16) {
218 if (LocVT == MVT::i32) {
231 if (LocVT == MVT::i64) {
246 if (LocVT == MVT::i64) {
257 if (LocVT == MVT::i64) {
270 if (LocVT == MVT::f16) {
283 if (LocVT == MVT::f32) {
296 if (LocVT == MVT::f64) {
309 if (LocVT == MVT::v1i64 ||
310 LocVT == MVT::v2i32 ||
311 LocVT == MVT::v4i16 ||
312 LocVT == MVT::v8i8 ||
313 LocVT == MVT::v1f64 ||
314 LocVT == MVT::v2f32 ||
315 LocVT == MVT::v4f16) {
328 if (LocVT == MVT::f128 ||
329 LocVT == MVT::v2i64 ||
330 LocVT == MVT::v4i32 ||
331 LocVT == MVT::v8i16 ||
332 LocVT == MVT::v16i8 ||
333 LocVT == MVT::v4f32 ||
334 LocVT == MVT::v2f64 ||
335 LocVT == MVT::v8f16) {
345 if (LocVT == MVT::i1 ||
346 LocVT == MVT::i8 ||
347 LocVT == MVT::i16 ||
348 LocVT == MVT::f16) {
354 if (LocVT == MVT::i32 ||
355 LocVT == MVT::f32) {
361 if (LocVT == MVT::i64 ||
362 LocVT == MVT::f64 ||
363 LocVT == MVT::v1f64 ||
364 LocVT == MVT::v2f32 ||
365 LocVT == MVT::v1i64 ||
366 LocVT == MVT::v2i32 ||
367 LocVT == MVT::v4i16 ||
368 LocVT == MVT::v8i8 ||
369 LocVT == MVT::v4f16) {
375 if (LocVT == MVT::f128 ||
376 LocVT == MVT::v2i64 ||
377 LocVT == MVT::v4i32 ||
378 LocVT == MVT::v8i16 ||
379 LocVT == MVT::v16i8 ||
380 LocVT == MVT::v4f32 ||
381 LocVT == MVT::v2f64 ||
382 LocVT == MVT::v8f16) {
396 if (LocVT == MVT::iPTR) {
401 if (LocVT == MVT::v2f32) {
406 if (LocVT == MVT::v2f64 ||
407 LocVT == MVT::v4f32 ||
408 LocVT == MVT::f128) {
414 if (LocVT == MVT::i64) {
428 if (LocVT == MVT::i64) {
437 if (LocVT == MVT::i64) {
450 if (LocVT == MVT::i1 ||
451 LocVT == MVT::i8 ||
452 LocVT == MVT::i16) {
462 if (LocVT == MVT::i32) {
475 if (LocVT == MVT::i64) {
490 if (LocVT == MVT::i64) {
501 if (LocVT == MVT::i64) {
514 if (LocVT == MVT::f16) {
527 if (LocVT == MVT::f32) {
540 if (LocVT == MVT::f64) {
553 if (LocVT == MVT::v1i64 ||
554 LocVT == MVT::v2i32 ||
555 LocVT == MVT::v4i16 ||
556 LocVT == MVT::v8i8 ||
557 LocVT == MVT::v1f64 ||
558 LocVT == MVT::v2f32 ||
559 LocVT == MVT::v4f16) {
572 if (LocVT == MVT::v2i64 ||
573 LocVT == MVT::v4i32 ||
574 LocVT == MVT::v8i16 ||
575 LocVT == MVT::v16i8 ||
576 LocVT == MVT::v4f32 ||
577 LocVT == MVT::v2f64 ||
578 LocVT == MVT::v8f16) {
588 if (ValVT == MVT::i1 || ValVT == MVT::i8) {
588 if (ValVT == MVT::i1 || ValVT == MVT::i8) {
594 if (ValVT == MVT::i16 || ValVT == MVT::f16) {
594 if (ValVT == MVT::i16 || ValVT == MVT::f16) {
600 if (LocVT == MVT::i32 ||
601 LocVT == MVT::f32) {
622 if (LocVT == MVT::i64 ||
623 LocVT == MVT::f64 ||
624 LocVT == MVT::v1f64 ||
625 LocVT == MVT::v2f32 ||
626 LocVT == MVT::v1i64 ||
627 LocVT == MVT::v2i32 ||
628 LocVT == MVT::v4i16 ||
629 LocVT == MVT::v8i8 ||
630 LocVT == MVT::v4f16) {
636 if (LocVT == MVT::v2i64 ||
637 LocVT == MVT::v4i32 ||
638 LocVT == MVT::v8i16 ||
639 LocVT == MVT::v16i8 ||
640 LocVT == MVT::v4f32 ||
641 LocVT == MVT::v2f64 ||
642 LocVT == MVT::v8f16) {
656 if (LocVT == MVT::v2f32) {
661 if (LocVT == MVT::v2f64 ||
662 LocVT == MVT::v4f32 ||
663 LocVT == MVT::f128) {
668 if (LocVT == MVT::i8 ||
669 LocVT == MVT::i16) {
679 if (LocVT == MVT::f16) {
691 if (LocVT == MVT::i32 ||
692 LocVT == MVT::f32) {
698 if (LocVT == MVT::i64) {
706 if (LocVT == MVT::i64 ||
707 LocVT == MVT::f64 ||
708 LocVT == MVT::v1i64 ||
709 LocVT == MVT::v2i32 ||
710 LocVT == MVT::v4i16 ||
711 LocVT == MVT::v8i8 ||
712 LocVT == MVT::v1f64 ||
713 LocVT == MVT::v2f32 ||
714 LocVT == MVT::v4f16) {
720 if (LocVT == MVT::v2i64 ||
721 LocVT == MVT::v4i32 ||
722 LocVT == MVT::v8i16 ||
723 LocVT == MVT::v16i8 ||
724 LocVT == MVT::v4f32 ||
725 LocVT == MVT::v2f64 ||
726 LocVT == MVT::v8f16) {
740 if (LocVT == MVT::iPTR) {
745 if (LocVT == MVT::v2f32) {
750 if (LocVT == MVT::v2f64 ||
751 LocVT == MVT::v4f32 ||
752 LocVT == MVT::f128) {
762 if (LocVT == MVT::i8 ||
763 LocVT == MVT::i16 ||
764 LocVT == MVT::i32) {
774 if (LocVT == MVT::f16 ||
775 LocVT == MVT::f32) {
780 if (LocVT == MVT::i64) {
788 if (LocVT == MVT::i64 ||
789 LocVT == MVT::f64 ||
790 LocVT == MVT::v1i64 ||
791 LocVT == MVT::v2i32 ||
792 LocVT == MVT::v4i16 ||
793 LocVT == MVT::v8i8 ||
794 LocVT == MVT::v1f64 ||
795 LocVT == MVT::v2f32 ||
796 LocVT == MVT::v4f16) {
802 if (LocVT == MVT::v2i64 ||
803 LocVT == MVT::v4i32 ||
804 LocVT == MVT::v8i16 ||
805 LocVT == MVT::v16i8 ||
806 LocVT == MVT::v4f32 ||
807 LocVT == MVT::v2f64 ||
808 LocVT == MVT::v8f16) {
822 if (LocVT == MVT::iPTR) {
827 if (LocVT == MVT::v1i64 ||
828 LocVT == MVT::v2i32 ||
829 LocVT == MVT::v4i16 ||
830 LocVT == MVT::v8i8 ||
831 LocVT == MVT::v2f32) {
836 if (LocVT == MVT::v2i64 ||
837 LocVT == MVT::v4i32 ||
838 LocVT == MVT::v8i16 ||
839 LocVT == MVT::v16i8 ||
840 LocVT == MVT::v4f32 ||
841 LocVT == MVT::f128) {
846 if (LocVT == MVT::v2f64) {
856 if (LocVT == MVT::f32) {
866 if (LocVT == MVT::f64) {
876 if (LocVT == MVT::i8 ||
877 LocVT == MVT::i16 ||
878 LocVT == MVT::i32) {
888 if (LocVT == MVT::i64) {
906 if (LocVT == MVT::i1 ||
907 LocVT == MVT::i8 ||
908 LocVT == MVT::i16) {
918 if (LocVT == MVT::i32) {
925 if (LocVT == MVT::i64) {
932 if (LocVT == MVT::i32 ||
933 LocVT == MVT::f32) {
939 if (LocVT == MVT::i64 ||
940 LocVT == MVT::f64) {
954 if (LocVT == MVT::i64) {
969 if (LocVT == MVT::f16 ||
970 LocVT == MVT::f32) {
975 if (LocVT == MVT::f64) {
991 if (LocVT == MVT::iPTR) {
996 if (LocVT == MVT::v2f32) {
1001 if (LocVT == MVT::v2f64 ||
1002 LocVT == MVT::v4f32) {
1013 if (LocVT == MVT::i64) {
1022 if (LocVT == MVT::v2i32 ||
1023 LocVT == MVT::v2f32 ||
1024 LocVT == MVT::v4i16 ||
1025 LocVT == MVT::v4f16 ||
1026 LocVT == MVT::v8i8) {
1033 if (LocVT == MVT::v2i64 ||
1034 LocVT == MVT::v2f64 ||
1035 LocVT == MVT::v4i32 ||
1036 LocVT == MVT::v4f32 ||
1037 LocVT == MVT::v8i16 ||
1038 LocVT == MVT::v8f16 ||
1039 LocVT == MVT::v16i8) {
1045 if (LocVT == MVT::i1 ||
1046 LocVT == MVT::i8 ||
1047 LocVT == MVT::i16) {
1057 if (LocVT == MVT::i32) {
1070 if (LocVT == MVT::i64) {
1083 if (LocVT == MVT::f16) {
1096 if (LocVT == MVT::f32) {
1109 if (LocVT == MVT::f64) {
1122 if (LocVT == MVT::v1i64 ||
1123 LocVT == MVT::v2i32 ||
1124 LocVT == MVT::v4i16 ||
1125 LocVT == MVT::v8i8 ||
1126 LocVT == MVT::v1f64 ||
1127 LocVT == MVT::v2f32 ||
1128 LocVT == MVT::v4f16) {
1141 if (LocVT == MVT::f128 ||
1142 LocVT == MVT::v2i64 ||
1143 LocVT == MVT::v4i32 ||
1144 LocVT == MVT::v8i16 ||
1145 LocVT == MVT::v16i8 ||
1146 LocVT == MVT::v4f32 ||
1147 LocVT == MVT::v2f64 ||
1148 LocVT == MVT::v8f16) {
1158 if (LocVT == MVT::nxv16i8 ||
1159 LocVT == MVT::nxv8i16 ||
1160 LocVT == MVT::nxv4i32 ||
1161 LocVT == MVT::nxv2i64 ||
1162 LocVT == MVT::nxv2f16 ||
1163 LocVT == MVT::nxv4f16 ||
1164 LocVT == MVT::nxv8f16 ||
1165 LocVT == MVT::nxv1f32 ||
1166 LocVT == MVT::nxv2f32 ||
1167 LocVT == MVT::nxv4f32 ||
1168 LocVT == MVT::nxv1f64 ||
1169 LocVT == MVT::nxv2f64) {
1179 if (LocVT == MVT::nxv2i1 ||
1180 LocVT == MVT::nxv4i1 ||
1181 LocVT == MVT::nxv8i1 ||
1182 LocVT == MVT::nxv16i1) {
1200 if (LocVT == MVT::i32) {
1213 if (LocVT == MVT::i64) {
1226 if (LocVT == MVT::f32) {
1239 if (LocVT == MVT::f64) {
gen/lib/Target/AArch64/AArch64GenFastISel.inc 9153 if (VT == MVT::i32 && Predicate_imm0_255(imm0))
gen/lib/Target/AMDGPU/AMDGPUGenCallingConv.inc 53 if (LocVT == MVT::i1) {
63 if (LocVT == MVT::i1 ||
64 LocVT == MVT::i8 ||
65 LocVT == MVT::i16) {
77 if (LocVT == MVT::i32 ||
78 LocVT == MVT::f32 ||
79 LocVT == MVT::i16 ||
80 LocVT == MVT::f16 ||
81 LocVT == MVT::v2i16 ||
82 LocVT == MVT::v2f16 ||
83 LocVT == MVT::i1) {
93 if (LocVT == MVT::i32 ||
94 LocVT == MVT::f32 ||
95 LocVT == MVT::v2i16 ||
96 LocVT == MVT::v2f16 ||
97 LocVT == MVT::i16 ||
98 LocVT == MVT::f16 ||
99 LocVT == MVT::i1) {
105 if (LocVT == MVT::i64 ||
106 LocVT == MVT::f64 ||
107 LocVT == MVT::v2i32 ||
108 LocVT == MVT::v2f32) {
114 if (LocVT == MVT::v3i32 ||
115 LocVT == MVT::v3f32) {
121 if (LocVT == MVT::v4i32 ||
122 LocVT == MVT::v4f32 ||
123 LocVT == MVT::v2i64 ||
124 LocVT == MVT::v2f64) {
130 if (LocVT == MVT::v5i32 ||
131 LocVT == MVT::v5f32) {
137 if (LocVT == MVT::v8i32 ||
138 LocVT == MVT::v8f32) {
144 if (LocVT == MVT::v16i32 ||
145 LocVT == MVT::v16f32) {
160 if (LocVT == MVT::f32 ||
161 LocVT == MVT::i32 ||
162 LocVT == MVT::f16 ||
163 LocVT == MVT::v2i16 ||
164 LocVT == MVT::v2f16) {
176 if (LocVT == MVT::f32 ||
177 LocVT == MVT::i32 ||
178 LocVT == MVT::f16 ||
179 LocVT == MVT::v2i16 ||
180 LocVT == MVT::v2f16) {
199 if (LocVT == MVT::i1) {
209 if (LocVT == MVT::i1 ||
210 LocVT == MVT::i16) {
222 if (LocVT == MVT::i32 ||
223 LocVT == MVT::f32 ||
224 LocVT == MVT::i16 ||
225 LocVT == MVT::f16 ||
226 LocVT == MVT::v2i16 ||
227 LocVT == MVT::v2f16) {
245 if (LocVT == MVT::i32) {
255 if (LocVT == MVT::f32 ||
256 LocVT == MVT::f16 ||
257 LocVT == MVT::v2f16) {
gen/lib/Target/AMDGPU/R600GenCallingConv.inc 19 if (LocVT == MVT::v4f32 ||
20 LocVT == MVT::v4i32) {
gen/lib/Target/ARC/ARCGenCallingConv.inc 21 if (LocVT == MVT::i8 ||
22 LocVT == MVT::i16) {
32 if (LocVT == MVT::i32 ||
33 LocVT == MVT::i64) {
43 if (LocVT == MVT::i64) {
49 if (LocVT == MVT::i32) {
63 if (LocVT == MVT::i32 ||
64 LocVT == MVT::i64) {
74 if (LocVT == MVT::i64) {
80 if (LocVT == MVT::i32) {
gen/lib/Target/ARM/ARMGenCallingConv.inc 63 if (LocVT == MVT::v1i64 ||
64 LocVT == MVT::v2i32 ||
65 LocVT == MVT::v4i16 ||
66 LocVT == MVT::v4f16 ||
67 LocVT == MVT::v4f16 ||
68 LocVT == MVT::v8i8 ||
69 LocVT == MVT::v2f32) {
74 if (LocVT == MVT::v2i64 ||
75 LocVT == MVT::v4i32 ||
76 LocVT == MVT::v8i16 ||
77 LocVT == MVT::v8f16 ||
78 LocVT == MVT::v8f16 ||
79 LocVT == MVT::v16i8 ||
80 LocVT == MVT::v4f32) {
86 if (LocVT == MVT::i32) {
95 if (LocVT == MVT::i32) {
103 if (LocVT == MVT::f64 ||
104 LocVT == MVT::v2f64) {
109 if (LocVT == MVT::f32) {
125 if (LocVT == MVT::i1 ||
126 LocVT == MVT::i8 ||
127 LocVT == MVT::i16) {
137 if (LocVT == MVT::i32) {
152 if (LocVT == MVT::i32) {
164 if (LocVT == MVT::i32) {
175 if (LocVT == MVT::i32) {
184 if (LocVT == MVT::f32) {
193 if (LocVT == MVT::f64) {
202 if (LocVT == MVT::v2f64) {
213 if (LocVT == MVT::v2f64) {
235 if (LocVT == MVT::v1i64 ||
236 LocVT == MVT::v2i32 ||
237 LocVT == MVT::v4i16 ||
238 LocVT == MVT::v4f16 ||
239 LocVT == MVT::v4f16 ||
240 LocVT == MVT::v8i8 ||
241 LocVT == MVT::v2f32) {
246 if (LocVT == MVT::v2i64 ||
247 LocVT == MVT::v4i32 ||
248 LocVT == MVT::v8i16 ||
249 LocVT == MVT::v8f16 ||
250 LocVT == MVT::v8f16 ||
251 LocVT == MVT::v16i8 ||
252 LocVT == MVT::v4f32) {
258 if (LocVT == MVT::i32) {
267 if (LocVT == MVT::i32) {
280 if (LocVT == MVT::v2f64) {
290 if (LocVT == MVT::f64) {
300 if (LocVT == MVT::f32) {
326 if (LocVT == MVT::i1 ||
327 LocVT == MVT::i8 ||
328 LocVT == MVT::i16) {
339 if (LocVT == MVT::i32) {
348 if (LocVT == MVT::i32) {
356 if (LocVT == MVT::v1i64 ||
357 LocVT == MVT::v2i32 ||
358 LocVT == MVT::v4i16 ||
359 LocVT == MVT::v4f16 ||
360 LocVT == MVT::v8i8 ||
361 LocVT == MVT::v2f32) {
366 if (LocVT == MVT::v2i64 ||
367 LocVT == MVT::v4i32 ||
368 LocVT == MVT::v8i16 ||
369 LocVT == MVT::v8f16 ||
370 LocVT == MVT::v16i8 ||
371 LocVT == MVT::v4f32) {
376 if (LocVT == MVT::f64 ||
377 LocVT == MVT::v2f64) {
382 if (LocVT == MVT::f32) {
387 if (LocVT == MVT::i32) {
397 if (LocVT == MVT::i32) {
403 if (LocVT == MVT::f64) {
409 if (LocVT == MVT::v2f64) {
423 if (LocVT == MVT::v1i64 ||
424 LocVT == MVT::v2i32 ||
425 LocVT == MVT::v4i16 ||
426 LocVT == MVT::v4f16 ||
427 LocVT == MVT::v8i8 ||
428 LocVT == MVT::v2f32) {
433 if (LocVT == MVT::v2i64 ||
434 LocVT == MVT::v4i32 ||
435 LocVT == MVT::v8i16 ||
436 LocVT == MVT::v8f16 ||
437 LocVT == MVT::v16i8 ||
438 LocVT == MVT::v4f32) {
443 if (LocVT == MVT::v2f64) {
453 if (LocVT == MVT::f64) {
463 if (LocVT == MVT::f32) {
473 if (LocVT == MVT::i8 ||
474 LocVT == MVT::i16) {
484 if (LocVT == MVT::i32) {
502 if (LocVT == MVT::i32) {
517 if (LocVT == MVT::v1i64 ||
518 LocVT == MVT::v2i32 ||
519 LocVT == MVT::v4i16 ||
520 LocVT == MVT::v4f16 ||
521 LocVT == MVT::v8i8 ||
522 LocVT == MVT::v2f32) {
527 if (LocVT == MVT::v2i64 ||
528 LocVT == MVT::v4i32 ||
529 LocVT == MVT::v8i16 ||
530 LocVT == MVT::v8f16 ||
531 LocVT == MVT::v16i8 ||
532 LocVT == MVT::v4f32) {
537 if (LocVT == MVT::v2f64) {
547 if (LocVT == MVT::f64) {
557 if (LocVT == MVT::f32) {
567 if (LocVT == MVT::f32) {
576 if (LocVT == MVT::f64) {
585 if (LocVT == MVT::v2f64) {
605 if (LocVT == MVT::v1i64 ||
606 LocVT == MVT::v2i32 ||
607 LocVT == MVT::v4i16 ||
608 LocVT == MVT::v4f16 ||
609 LocVT == MVT::v4f16 ||
610 LocVT == MVT::v8i8 ||
611 LocVT == MVT::v2f32) {
616 if (LocVT == MVT::v2i64 ||
617 LocVT == MVT::v4i32 ||
618 LocVT == MVT::v8i16 ||
619 LocVT == MVT::v8f16 ||
620 LocVT == MVT::v8f16 ||
621 LocVT == MVT::v16i8 ||
622 LocVT == MVT::v4f32) {
628 if (LocVT == MVT::i32) {
637 if (LocVT == MVT::i32) {
645 if (LocVT == MVT::f64 ||
646 LocVT == MVT::v2f64) {
651 if (LocVT == MVT::f32) {
667 if (LocVT == MVT::i1 ||
668 LocVT == MVT::i8 ||
669 LocVT == MVT::i16) {
679 if (LocVT == MVT::i32) {
689 if (LocVT == MVT::i64) {
710 if (LocVT == MVT::v1i64 ||
711 LocVT == MVT::v2i32 ||
712 LocVT == MVT::v4i16 ||
713 LocVT == MVT::v4f16 ||
714 LocVT == MVT::v4f16 ||
715 LocVT == MVT::v8i8 ||
716 LocVT == MVT::v2f32) {
721 if (LocVT == MVT::v2i64 ||
722 LocVT == MVT::v4i32 ||
723 LocVT == MVT::v8i16 ||
724 LocVT == MVT::v8f16 ||
725 LocVT == MVT::v8f16 ||
726 LocVT == MVT::v16i8 ||
727 LocVT == MVT::v4f32) {
733 if (LocVT == MVT::i32) {
742 if (LocVT == MVT::i32) {
750 if (LocVT == MVT::v2f64) {
760 if (LocVT == MVT::f64) {
770 if (LocVT == MVT::f32) {
791 if (LocVT == MVT::i1 ||
792 LocVT == MVT::i8 ||
793 LocVT == MVT::i16) {
803 if (LocVT == MVT::f32) {
809 if (LocVT == MVT::i32) {
818 if (LocVT == MVT::i32) {
826 if (LocVT == MVT::v1i64 ||
827 LocVT == MVT::v2i32 ||
828 LocVT == MVT::v4i16 ||
829 LocVT == MVT::v4f16 ||
830 LocVT == MVT::v8i8 ||
831 LocVT == MVT::v2f32) {
836 if (LocVT == MVT::v2i64 ||
837 LocVT == MVT::v4i32 ||
838 LocVT == MVT::v8i16 ||
839 LocVT == MVT::v8f16 ||
840 LocVT == MVT::v16i8 ||
841 LocVT == MVT::v4f32) {
846 if (LocVT == MVT::f64 ||
847 LocVT == MVT::v2f64) {
852 if (LocVT == MVT::i32) {
862 if (LocVT == MVT::i64) {
883 if (LocVT == MVT::v1i64 ||
884 LocVT == MVT::v2i32 ||
885 LocVT == MVT::v4i16 ||
886 LocVT == MVT::v4f16 ||
887 LocVT == MVT::v8i8 ||
888 LocVT == MVT::v2f32) {
893 if (LocVT == MVT::v2i64 ||
894 LocVT == MVT::v4i32 ||
895 LocVT == MVT::v8i16 ||
896 LocVT == MVT::v8f16 ||
897 LocVT == MVT::v16i8 ||
898 LocVT == MVT::v4f32) {
903 if (LocVT == MVT::v2f64) {
913 if (LocVT == MVT::f64) {
923 if (LocVT == MVT::f32) {
gen/lib/Target/ARM/ARMGenFastISel.inc 6125 if (VT == MVT::i32 && Predicate_mod_imm(imm1))
6129 if (VT == MVT::i32 && Predicate_imm0_7(imm1))
6133 if (VT == MVT::i32 && Predicate_imm8_255(imm1))
6137 if (VT == MVT::i32 && Predicate_imm0_255(imm1))
6141 if (VT == MVT::i32 && Predicate_t2_so_imm(imm1))
6145 if (VT == MVT::i32 && Predicate_imm0_4095(imm1))
6149 if (VT == MVT::i32 && Predicate_imm1_31(imm1))
6153 if (VT == MVT::i32 && Predicate_imm0_31(imm1))
6157 if (VT == MVT::i32 && Predicate_shr_imm8(imm1))
6161 if (VT == MVT::i32 && Predicate_shr_imm16(imm1))
6165 if (VT == MVT::i32 && Predicate_shr_imm32(imm1))
6169 if (VT == MVT::i32 && Predicate_VectorIndex32(imm1))
6173 if (VT == MVT::i32 && Predicate_imm0_15(imm1))
gen/lib/Target/AVR/AVRGenCallingConv.inc 27 if (LocVT == MVT::i8) {
37 if (LocVT == MVT::i16) {
67 if (LocVT == MVT::i8) {
74 if (LocVT == MVT::i16) {
92 if (LocVT == MVT::i8) {
102 if (LocVT == MVT::i16) {
gen/lib/Target/BPF/BPFGenCallingConv.inc 27 if (LocVT == MVT::i32) {
40 if (LocVT == MVT::i64) {
65 if (LocVT == MVT::i8 ||
66 LocVT == MVT::i16 ||
67 LocVT == MVT::i32) {
77 if (LocVT == MVT::i64) {
99 if (LocVT == MVT::i32) {
106 if (LocVT == MVT::i64) {
121 if (LocVT == MVT::i64) {
gen/lib/Target/Hexagon/HexagonGenCallingConv.inc 30 if (LocVT == MVT::i1 ||
31 LocVT == MVT::i8 ||
32 LocVT == MVT::i16) {
42 if (LocVT == MVT::f32) {
47 if (LocVT == MVT::f64) {
62 if (LocVT == MVT::i32) {
69 if (LocVT == MVT::i32 ||
70 LocVT == MVT::v2i16 ||
71 LocVT == MVT::v4i8) {
81 if (LocVT == MVT::i64 ||
82 LocVT == MVT::v2i32 ||
83 LocVT == MVT::v4i16 ||
84 LocVT == MVT::v8i8) {
89 if (LocVT == MVT::i64 ||
90 LocVT == MVT::v2i32 ||
91 LocVT == MVT::v4i16 ||
92 LocVT == MVT::v8i8) {
113 if (LocVT == MVT::i32 ||
114 LocVT == MVT::v2i16 ||
115 LocVT == MVT::v4i8) {
121 if (LocVT == MVT::i64 ||
122 LocVT == MVT::v2i32 ||
123 LocVT == MVT::v4i16 ||
124 LocVT == MVT::v8i8) {
139 if (LocVT == MVT::v16i32 ||
140 LocVT == MVT::v32i16 ||
141 LocVT == MVT::v64i8) {
153 if (LocVT == MVT::v32i32 ||
154 LocVT == MVT::v64i16 ||
155 LocVT == MVT::v128i8) {
167 if (LocVT == MVT::v16i32 ||
168 LocVT == MVT::v32i16 ||
169 LocVT == MVT::v64i8) {
177 if (LocVT == MVT::v32i32 ||
178 LocVT == MVT::v64i16 ||
179 LocVT == MVT::v128i8) {
187 if (LocVT == MVT::v32i32 ||
188 LocVT == MVT::v64i16 ||
189 LocVT == MVT::v128i8) {
201 if (LocVT == MVT::v64i32 ||
202 LocVT == MVT::v128i16 ||
203 LocVT == MVT::v256i8) {
215 if (LocVT == MVT::v32i32 ||
216 LocVT == MVT::v64i16 ||
217 LocVT == MVT::v128i8) {
225 if (LocVT == MVT::v64i32 ||
226 LocVT == MVT::v128i16 ||
227 LocVT == MVT::v256i8) {
245 if (LocVT == MVT::i1 ||
246 LocVT == MVT::i8 ||
247 LocVT == MVT::i16) {
257 if (LocVT == MVT::f32) {
262 if (LocVT == MVT::f64) {
277 if (LocVT == MVT::i32 ||
278 LocVT == MVT::v2i16 ||
279 LocVT == MVT::v4i8) {
289 if (LocVT == MVT::i64 ||
290 LocVT == MVT::v2i32 ||
291 LocVT == MVT::v4i16 ||
292 LocVT == MVT::v8i8) {
308 if (LocVT == MVT::v16i32 ||
309 LocVT == MVT::v32i16 ||
310 LocVT == MVT::v64i8) {
319 if (LocVT == MVT::v32i32 ||
320 LocVT == MVT::v64i16 ||
321 LocVT == MVT::v128i8) {
330 if (LocVT == MVT::v32i32 ||
331 LocVT == MVT::v64i16 ||
332 LocVT == MVT::v128i8) {
341 if (LocVT == MVT::v64i32 ||
342 LocVT == MVT::v128i16 ||
343 LocVT == MVT::v256i8) {
gen/lib/Target/Lanai/LanaiGenCallingConv.inc 24 if (LocVT == MVT::i8 ||
25 LocVT == MVT::i16) {
37 if (LocVT == MVT::i32) {
61 if (LocVT == MVT::i8 ||
62 LocVT == MVT::i16) {
73 if (LocVT == MVT::i32) {
96 if (LocVT == MVT::i32) {
gen/lib/Target/MSP430/MSP430GenCallingConv.inc 26 if (LocVT == MVT::i8) {
36 if (LocVT == MVT::i16) {
50 if (LocVT == MVT::i8) {
60 if (LocVT == MVT::i16) {
gen/lib/Target/Mips/MipsGenCallingConv.inc 95 if (LocVT == MVT::i32) {
113 if (LocVT == MVT::i8 ||
114 LocVT == MVT::i16 ||
115 LocVT == MVT::i32 ||
116 LocVT == MVT::i64) {
130 if (LocVT == MVT::i8 ||
131 LocVT == MVT::i16 ||
132 LocVT == MVT::i32) {
145 if (LocVT == MVT::i32) {
151 if (LocVT == MVT::i64) {
164 if (LocVT == MVT::f32) {
177 if (LocVT == MVT::f64) {
190 if (LocVT == MVT::f32) {
196 if (LocVT == MVT::i64 ||
197 LocVT == MVT::f64) {
211 if (LocVT == MVT::i64) {
221 if (LocVT == MVT::f64) {
231 if (LocVT == MVT::i64 ||
232 LocVT == MVT::f64) {
269 if (LocVT == MVT::i8 ||
270 LocVT == MVT::i16 ||
271 LocVT == MVT::i32 ||
272 LocVT == MVT::i64) {
286 if (LocVT == MVT::i8 ||
287 LocVT == MVT::i16 ||
288 LocVT == MVT::i32) {
298 if (LocVT == MVT::f32) {
308 if (LocVT == MVT::i64 ||
309 LocVT == MVT::f64) {
319 if (LocVT == MVT::f32) {
325 if (LocVT == MVT::i64 ||
326 LocVT == MVT::f64) {
340 if (LocVT == MVT::i1 ||
341 LocVT == MVT::i8 ||
342 LocVT == MVT::i16) {
352 if (LocVT == MVT::i32 ||
353 LocVT == MVT::f32) {
359 if (LocVT == MVT::f64) {
391 if (LocVT == MVT::f64) {
403 if (LocVT == MVT::f64) {
417 if (LocVT == MVT::f64) {
431 if (LocVT == MVT::f64) {
470 if (LocVT == MVT::i8 ||
471 LocVT == MVT::i16) {
481 if (LocVT == MVT::i32) {
493 if (LocVT == MVT::i32) {
505 if (LocVT == MVT::f32) {
517 if (LocVT == MVT::f32) {
529 if (LocVT == MVT::i32 ||
530 LocVT == MVT::f32) {
564 if (LocVT == MVT::i64) {
616 if (LocVT == MVT::i64) {
623 if (LocVT == MVT::i64) {
703 if (LocVT == MVT::i64) {
711 if (LocVT == MVT::i8 ||
712 LocVT == MVT::i16 ||
713 LocVT == MVT::i32 ||
714 LocVT == MVT::i64) {
728 if (LocVT == MVT::i8 ||
729 LocVT == MVT::i16 ||
730 LocVT == MVT::i32 ||
731 LocVT == MVT::i64) {
744 if (LocVT == MVT::i64) {
754 if (LocVT == MVT::f32) {
764 if (LocVT == MVT::f64) {
782 if (LocVT == MVT::i1 ||
783 LocVT == MVT::i8 ||
784 LocVT == MVT::i16) {
795 if (LocVT == MVT::i32) {
806 if (LocVT == MVT::f32) {
816 if (LocVT == MVT::f64) {
828 if (LocVT == MVT::f64) {
gen/lib/Target/Mips/MipsGenFastISel.inc 3561 if (VT == MVT::i32 && Predicate_immZExt5(imm1))
3565 if (VT == MVT::i32 && Predicate_immZExt6(imm1))
3569 if (VT == MVT::iPTR && Predicate_immZExt2Ptr(imm1))
3573 if (VT == MVT::iPTR && Predicate_immZExt1Ptr(imm1))
3577 if (VT == MVT::i32 && Predicate_immZExt4(imm1))
3581 if (VT == MVT::i32 && Predicate_immSExtAddiur2(imm1))
3585 if (VT == MVT::i32 && Predicate_immSExtAddius5(imm1))
3589 if (VT == MVT::i32 && Predicate_immZExtAndi16(imm1))
3593 if (VT == MVT::i32 && Predicate_immZExt2Shift(imm1))
gen/lib/Target/PowerPC/PPCGenCallingConv.inc 45 if (LocVT == MVT::v4f64 ||
46 LocVT == MVT::v4f32 ||
47 LocVT == MVT::v4i1) {
59 if (LocVT == MVT::v16i8 ||
60 LocVT == MVT::v8i16 ||
61 LocVT == MVT::v4i32 ||
62 LocVT == MVT::v2i64 ||
63 LocVT == MVT::v1i128 ||
64 LocVT == MVT::v4f32 ||
65 LocVT == MVT::v2f64) {
77 if (LocVT == MVT::f128) {
116 if (LocVT == MVT::i1) {
126 if (LocVT == MVT::i32) {
137 if (LocVT == MVT::i32) {
146 if (LocVT == MVT::f64) {
169 if (LocVT == MVT::i32) {
179 if (LocVT == MVT::f64) {
186 if (LocVT == MVT::f32 ||
187 LocVT == MVT::f64) {
199 if (LocVT == MVT::f64) {
206 if (LocVT == MVT::f32) {
218 if (LocVT == MVT::i32) {
226 if (LocVT == MVT::i32) {
232 if (LocVT == MVT::f32 ||
233 LocVT == MVT::f64) {
241 if (LocVT == MVT::f32) {
249 if (LocVT == MVT::f64) {
257 if (LocVT == MVT::v4f64 ||
258 LocVT == MVT::v4i1) {
264 if (LocVT == MVT::v16i8 ||
265 LocVT == MVT::v8i16 ||
266 LocVT == MVT::v4i32 ||
267 LocVT == MVT::v4f32 ||
268 LocVT == MVT::v2f64 ||
269 LocVT == MVT::v2i64) {
275 if (LocVT == MVT::f128) {
318 if (LocVT == MVT::i1) {
328 if (LocVT == MVT::i8) {
338 if (LocVT == MVT::i16) {
348 if (LocVT == MVT::i32) {
358 if (LocVT == MVT::i64) {
368 if (LocVT == MVT::f32 ||
369 LocVT == MVT::f64) {
392 if (LocVT == MVT::i32 ||
393 LocVT == MVT::i1) {
405 if (LocVT == MVT::i1) {
417 if (LocVT == MVT::i32) {
427 if (LocVT == MVT::i64) {
437 if (LocVT == MVT::i128) {
448 if (LocVT == MVT::f32) {
460 if (LocVT == MVT::f64) {
472 if (LocVT == MVT::f32) {
484 if (LocVT == MVT::f64) {
490 if (LocVT == MVT::f128) {
502 if (LocVT == MVT::v4f64 ||
503 LocVT == MVT::v4f32 ||
504 LocVT == MVT::v4i1) {
516 if (LocVT == MVT::v16i8 ||
517 LocVT == MVT::v8i16 ||
518 LocVT == MVT::v4i32 ||
519 LocVT == MVT::v2i64 ||
520 LocVT == MVT::v1i128 ||
521 LocVT == MVT::v4f32 ||
522 LocVT == MVT::v2f64) {
558 if (LocVT == MVT::i1) {
568 if (LocVT == MVT::i8) {
578 if (LocVT == MVT::i16) {
588 if (LocVT == MVT::i32) {
598 if (LocVT == MVT::i64) {
608 if (LocVT == MVT::i128) {
618 if (LocVT == MVT::f32) {
628 if (LocVT == MVT::f64) {
638 if (LocVT == MVT::f128) {
650 if (LocVT == MVT::v4f64 ||
651 LocVT == MVT::v4f32 ||
652 LocVT == MVT::v4i1) {
664 if (LocVT == MVT::v16i8 ||
665 LocVT == MVT::v8i16 ||
666 LocVT == MVT::v4i32 ||
667 LocVT == MVT::v2i64 ||
668 LocVT == MVT::v1i128 ||
669 LocVT == MVT::v4f32 ||
670 LocVT == MVT::v2f64) {
690 if (LocVT == MVT::i32 ||
691 LocVT == MVT::i1) {
703 if (LocVT == MVT::i1) {
715 if (LocVT == MVT::i32) {
722 if (LocVT == MVT::i64) {
729 if (LocVT == MVT::i128) {
736 if (LocVT == MVT::f32) {
743 if (LocVT == MVT::f64) {
750 if (LocVT == MVT::f128) {
759 if (LocVT == MVT::v4f64 ||
760 LocVT == MVT::v4f32 ||
761 LocVT == MVT::v4i1) {
770 if (LocVT == MVT::v16i8 ||
771 LocVT == MVT::v8i16 ||
772 LocVT == MVT::v4i32 ||
773 LocVT == MVT::v2i64 ||
774 LocVT == MVT::v1i128 ||
775 LocVT == MVT::v4f32 ||
776 LocVT == MVT::v2f64) {
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3374 if (VT == MVT::i32 && Predicate_imm32SExt16(imm1))
3378 if (VT == MVT::i64 && Predicate_imm64SExt16(imm1))
gen/lib/Target/Sparc/SparcGenCallingConv.inc 32 if (LocVT == MVT::i32 ||
33 LocVT == MVT::f32) {
43 if (LocVT == MVT::f64) {
48 if (LocVT == MVT::v2i32) {
66 if (LocVT == MVT::i32 ||
67 LocVT == MVT::f32) {
73 if (LocVT == MVT::i32) {
94 if (LocVT == MVT::i32) {
104 if (LocVT == MVT::f32) {
114 if (LocVT == MVT::f64) {
124 if (LocVT == MVT::v2i32) {
137 if (LocVT == MVT::f32) {
gen/lib/Target/SystemZ/SystemZGenCallingConv.inc 21 if (LocVT == MVT::i32) {
34 if (LocVT == MVT::i64) {
43 if (LocVT == MVT::i64) {
51 if (LocVT == MVT::f128) {
56 if (LocVT == MVT::i64) {
61 if (LocVT == MVT::i32) {
71 if (LocVT == MVT::i64) {
81 if (LocVT == MVT::f32) {
91 if (LocVT == MVT::f64) {
102 if (LocVT == MVT::v16i8 ||
103 LocVT == MVT::v8i16 ||
104 LocVT == MVT::v4i32 ||
105 LocVT == MVT::v2i64 ||
106 LocVT == MVT::v4f32 ||
107 LocVT == MVT::v2f64) {
121 if (LocVT == MVT::v16i8 ||
122 LocVT == MVT::v8i16 ||
123 LocVT == MVT::v4i32 ||
124 LocVT == MVT::v2i64 ||
125 LocVT == MVT::v4f32 ||
126 LocVT == MVT::v2f64) {
135 if (LocVT == MVT::v16i8 ||
136 LocVT == MVT::v8i16 ||
137 LocVT == MVT::v4i32 ||
138 LocVT == MVT::v2i64 ||
139 LocVT == MVT::v4f32 ||
140 LocVT == MVT::v2f64) {
147 if (LocVT == MVT::i32 ||
148 LocVT == MVT::i64 ||
149 LocVT == MVT::f32 ||
150 LocVT == MVT::f64) {
164 if (LocVT == MVT::i32) {
177 if (LocVT == MVT::i64) {
185 if (LocVT == MVT::i32) {
195 if (LocVT == MVT::i64) {
205 if (LocVT == MVT::f32) {
215 if (LocVT == MVT::f64) {
226 if (LocVT == MVT::v16i8 ||
227 LocVT == MVT::v8i16 ||
228 LocVT == MVT::v4i32 ||
229 LocVT == MVT::v2i64 ||
230 LocVT == MVT::v4f32 ||
231 LocVT == MVT::v2f64) {
gen/lib/Target/X86/X86GenCallingConv.inc 171 if (LocVT == MVT::i32) {
183 if (LocVT == MVT::i64) {
195 if (LocVT == MVT::i32) {
207 if (LocVT == MVT::i64) {
219 if (LocVT == MVT::i32) {
225 if (LocVT == MVT::f32 ||
226 LocVT == MVT::f64 ||
227 LocVT == MVT::v4i32 ||
228 LocVT == MVT::v2i64 ||
229 LocVT == MVT::v4f32 ||
230 LocVT == MVT::v2f64) {
240 if (LocVT == MVT::v8f32 ||
241 LocVT == MVT::v4f64 ||
242 LocVT == MVT::v8i32 ||
243 LocVT == MVT::v4i64) {
253 if (LocVT == MVT::v16f32 ||
254 LocVT == MVT::v8f64 ||
255 LocVT == MVT::v16i32 ||
256 LocVT == MVT::v8i64) {
266 if (LocVT == MVT::v16i1 ||
267 LocVT == MVT::v8i1) {
382 if (LocVT == MVT::i1 ||
383 LocVT == MVT::i8 ||
384 LocVT == MVT::i16 ||
385 LocVT == MVT::v1i1) {
404 if (LocVT == MVT::i32) {
434 if (LocVT == MVT::f32 ||
435 LocVT == MVT::f64) {
450 if (LocVT == MVT::x86mmx) {
461 if (LocVT == MVT::i32 ||
462 LocVT == MVT::f32) {
468 if (LocVT == MVT::f64) {
474 if (LocVT == MVT::f80) {
481 if (LocVT == MVT::v2i1) {
491 if (LocVT == MVT::v4i1) {
501 if (LocVT == MVT::v8i1) {
511 if (LocVT == MVT::v16i1) {
521 if (LocVT == MVT::v32i1) {
531 if (LocVT == MVT::v64i1) {
541 if (LocVT == MVT::x86mmx) {
568 if (LocVT == MVT::i1 ||
569 LocVT == MVT::i8 ||
570 LocVT == MVT::i16 ||
571 LocVT == MVT::v1i1) {
588 if (LocVT == MVT::i32) {
599 if (LocVT == MVT::f32 ||
600 LocVT == MVT::f64) {
613 if (LocVT == MVT::f64) {
630 if (LocVT == MVT::i1) {
648 if (LocVT == MVT::i8) {
660 if (LocVT == MVT::i16) {
672 if (LocVT == MVT::i32) {
694 if (LocVT == MVT::i8 ||
695 LocVT == MVT::i16) {
705 if (LocVT == MVT::i32) {
723 if (LocVT == MVT::i8 ||
724 LocVT == MVT::i16) {
734 if (LocVT == MVT::i32) {
744 if (LocVT == MVT::i32 ||
745 LocVT == MVT::f32) {
764 if (LocVT == MVT::i1 ||
765 LocVT == MVT::i8 ||
766 LocVT == MVT::i16 ||
767 LocVT == MVT::v1i1) {
778 if (LocVT == MVT::i32) {
807 if (LocVT == MVT::i1 ||
808 LocVT == MVT::i8 ||
809 LocVT == MVT::i16 ||
810 LocVT == MVT::v1i1) {
820 if (LocVT == MVT::v8i1 ||
821 LocVT == MVT::v16i1 ||
822 LocVT == MVT::v32i1) {
832 if (LocVT == MVT::i32) {
842 if (LocVT == MVT::i64) {
849 if (LocVT == MVT::v64i1) {
860 if (LocVT == MVT::i64) {
869 if (LocVT == MVT::i64) {
875 if (LocVT == MVT::f32 ||
876 LocVT == MVT::f64 ||
877 LocVT == MVT::f128) {
889 if (LocVT == MVT::f80) {
896 if (LocVT == MVT::v16i8 ||
897 LocVT == MVT::v8i16 ||
898 LocVT == MVT::v4i32 ||
899 LocVT == MVT::v2i64 ||
900 LocVT == MVT::v4f32 ||
901 LocVT == MVT::v2f64) {
913 if (LocVT == MVT::v32i8 ||
914 LocVT == MVT::v16i16 ||
915 LocVT == MVT::v8i32 ||
916 LocVT == MVT::v4i64 ||
917 LocVT == MVT::v8f32 ||
918 LocVT == MVT::v4f64) {
930 if (LocVT == MVT::v64i8 ||
931 LocVT == MVT::v32i16 ||
932 LocVT == MVT::v16i32 ||
933 LocVT == MVT::v8i64 ||
934 LocVT == MVT::v16f32 ||
935 LocVT == MVT::v8f64) {
948 if (LocVT == MVT::i32 ||
949 LocVT == MVT::i64 ||
950 LocVT == MVT::f32 ||
951 LocVT == MVT::f64) {
958 if (LocVT == MVT::i32 ||
959 LocVT == MVT::f32) {
965 if (LocVT == MVT::i64 ||
966 LocVT == MVT::f64) {
973 if (LocVT == MVT::x86mmx) {
980 if (LocVT == MVT::x86mmx) {
986 if (LocVT == MVT::f80 ||
987 LocVT == MVT::f128) {
995 if (LocVT == MVT::v16i8 ||
996 LocVT == MVT::v8i16 ||
997 LocVT == MVT::v4i32 ||
998 LocVT == MVT::v2i64 ||
999 LocVT == MVT::v4f32 ||
1000 LocVT == MVT::v2f64) {
1006 if (LocVT == MVT::v32i8 ||
1007 LocVT == MVT::v16i16 ||
1008 LocVT == MVT::v8i32 ||
1009 LocVT == MVT::v4i64 ||
1010 LocVT == MVT::v8f32 ||
1011 LocVT == MVT::v4f64) {
1017 if (LocVT == MVT::v64i8 ||
1018 LocVT == MVT::v32i16 ||
1019 LocVT == MVT::v16i32 ||
1020 LocVT == MVT::v8i64 ||
1021 LocVT == MVT::v16f32 ||
1022 LocVT == MVT::v8f64) {
1052 if (LocVT == MVT::i32) {
1070 if (LocVT == MVT::i1 ||
1071 LocVT == MVT::i8 ||
1072 LocVT == MVT::i16 ||
1073 LocVT == MVT::v1i1) {
1094 if (LocVT == MVT::i1 ||
1095 LocVT == MVT::i8 ||
1096 LocVT == MVT::i16 ||
1097 LocVT == MVT::v1i1) {
1124 if (LocVT == MVT::v16i8 ||
1125 LocVT == MVT::v8i16 ||
1126 LocVT == MVT::v4i32 ||
1127 LocVT == MVT::v2i64 ||
1128 LocVT == MVT::v4f32 ||
1129 LocVT == MVT::v2f64) {
1135 if (LocVT == MVT::v32i8 ||
1136 LocVT == MVT::v16i16 ||
1137 LocVT == MVT::v8i32 ||
1138 LocVT == MVT::v4i64 ||
1139 LocVT == MVT::v8f32 ||
1140 LocVT == MVT::v4f64) {
1146 if (LocVT == MVT::v64i8 ||
1147 LocVT == MVT::v32i16 ||
1148 LocVT == MVT::v16i32 ||
1149 LocVT == MVT::v8i64 ||
1150 LocVT == MVT::v16f32 ||
1151 LocVT == MVT::v8f64) {
1166 if (LocVT == MVT::v16i8 ||
1167 LocVT == MVT::v8i16 ||
1168 LocVT == MVT::v4i32 ||
1169 LocVT == MVT::v2i64 ||
1170 LocVT == MVT::v4f32 ||
1171 LocVT == MVT::v2f64) {
1183 if (LocVT == MVT::v32i8 ||
1184 LocVT == MVT::v16i16 ||
1185 LocVT == MVT::v8i32 ||
1186 LocVT == MVT::v4i64 ||
1187 LocVT == MVT::v8f32 ||
1188 LocVT == MVT::v4f64) {
1202 if (LocVT == MVT::v64i8 ||
1203 LocVT == MVT::v32i16 ||
1204 LocVT == MVT::v16i32 ||
1205 LocVT == MVT::v8i64 ||
1206 LocVT == MVT::v16f32 ||
1207 LocVT == MVT::v8f64) {
1230 if (LocVT == MVT::v16i8 ||
1231 LocVT == MVT::v8i16 ||
1232 LocVT == MVT::v4i32 ||
1233 LocVT == MVT::v2i64 ||
1234 LocVT == MVT::v4f32 ||
1235 LocVT == MVT::v2f64) {
1247 if (LocVT == MVT::v32i8 ||
1248 LocVT == MVT::v16i16 ||
1249 LocVT == MVT::v8i32 ||
1250 LocVT == MVT::v4i64 ||
1251 LocVT == MVT::v8f32 ||
1252 LocVT == MVT::v4f64) {
1266 if (LocVT == MVT::v64i8 ||
1267 LocVT == MVT::v32i16 ||
1268 LocVT == MVT::v16i32 ||
1269 LocVT == MVT::v8i64 ||
1270 LocVT == MVT::v16f32 ||
1271 LocVT == MVT::v8f64) {
1387 if (LocVT == MVT::i1 ||
1388 LocVT == MVT::i8 ||
1389 LocVT == MVT::i16 ||
1390 LocVT == MVT::v1i1) {
1417 if (LocVT == MVT::i64) {
1426 if (LocVT == MVT::i64) {
1436 if (LocVT == MVT::i64) {
1445 if (LocVT == MVT::i32) {
1455 if (LocVT == MVT::i64) {
1465 if (LocVT == MVT::x86mmx) {
1479 if (LocVT == MVT::v2i1) {
1489 if (LocVT == MVT::v4i1) {
1499 if (LocVT == MVT::v8i1) {
1509 if (LocVT == MVT::v16i1) {
1519 if (LocVT == MVT::v32i1) {
1529 if (LocVT == MVT::v64i1) {
1539 if (LocVT == MVT::f32 ||
1540 LocVT == MVT::f64 ||
1541 LocVT == MVT::f128 ||
1542 LocVT == MVT::v16i8 ||
1543 LocVT == MVT::v8i16 ||
1544 LocVT == MVT::v4i32 ||
1545 LocVT == MVT::v2i64 ||
1546 LocVT == MVT::v4f32 ||
1547 LocVT == MVT::v2f64) {
1560 if (LocVT == MVT::v32i8 ||
1561 LocVT == MVT::v16i16 ||
1562 LocVT == MVT::v8i32 ||
1563 LocVT == MVT::v4i64 ||
1564 LocVT == MVT::v8f32 ||
1565 LocVT == MVT::v4f64) {
1579 if (LocVT == MVT::v64i8 ||
1580 LocVT == MVT::v32i16 ||
1581 LocVT == MVT::v16i32 ||
1582 LocVT == MVT::v8i64 ||
1583 LocVT == MVT::v16f32 ||
1584 LocVT == MVT::v8f64) {
1597 if (LocVT == MVT::i32 ||
1598 LocVT == MVT::i64 ||
1599 LocVT == MVT::f32 ||
1600 LocVT == MVT::f64) {
1606 if (LocVT == MVT::f80 ||
1607 LocVT == MVT::f128) {
1615 if (LocVT == MVT::v16i8 ||
1616 LocVT == MVT::v8i16 ||
1617 LocVT == MVT::v4i32 ||
1618 LocVT == MVT::v2i64 ||
1619 LocVT == MVT::v4f32 ||
1620 LocVT == MVT::v2f64) {
1626 if (LocVT == MVT::v32i8 ||
1627 LocVT == MVT::v16i16 ||
1628 LocVT == MVT::v8i32 ||
1629 LocVT == MVT::v4i64 ||
1630 LocVT == MVT::v8f32 ||
1631 LocVT == MVT::v4f64) {
1637 if (LocVT == MVT::v64i8 ||
1638 LocVT == MVT::v32i16 ||
1639 LocVT == MVT::v16i32 ||
1640 LocVT == MVT::v8i64 ||
1641 LocVT == MVT::v16f32 ||
1642 LocVT == MVT::v8f64) {
1656 if (LocVT == MVT::i8 ||
1657 LocVT == MVT::i16 ||
1658 LocVT == MVT::i32) {
1668 if (LocVT == MVT::i64) {
1678 if (LocVT == MVT::f32 ||
1679 LocVT == MVT::f64 ||
1680 LocVT == MVT::v16i8 ||
1681 LocVT == MVT::v8i16 ||
1682 LocVT == MVT::v4i32 ||
1683 LocVT == MVT::v2i64 ||
1684 LocVT == MVT::v4f32 ||
1685 LocVT == MVT::v2f64) {
1697 if (LocVT == MVT::v32i8 ||
1698 LocVT == MVT::v16i16 ||
1699 LocVT == MVT::v8i32 ||
1700 LocVT == MVT::v4i64 ||
1701 LocVT == MVT::v8f32 ||
1702 LocVT == MVT::v4f64) {
1714 if (LocVT == MVT::v64i8 ||
1715 LocVT == MVT::v32i16 ||
1716 LocVT == MVT::v16i32 ||
1717 LocVT == MVT::v8i64 ||
1718 LocVT == MVT::v16f32 ||
1719 LocVT == MVT::v8f64) {
1739 if (LocVT == MVT::i64) {
1757 if (LocVT == MVT::i64) {
1775 if (LocVT == MVT::i8 ||
1776 LocVT == MVT::i16 ||
1777 LocVT == MVT::i32) {
1787 if (LocVT == MVT::i64) {
1797 if (LocVT == MVT::i32 ||
1798 LocVT == MVT::i64 ||
1799 LocVT == MVT::f32 ||
1800 LocVT == MVT::f64) {
1814 if (LocVT == MVT::i8 ||
1815 LocVT == MVT::i16) {
1825 if (LocVT == MVT::i32) {
1832 if (LocVT == MVT::i64) {
1839 if (LocVT == MVT::i32 ||
1840 LocVT == MVT::f32) {
1846 if (LocVT == MVT::i64 ||
1847 LocVT == MVT::f64) {
1873 if (LocVT == MVT::i1 ||
1874 LocVT == MVT::i8 ||
1875 LocVT == MVT::i16 ||
1876 LocVT == MVT::v1i1) {
1886 if (LocVT == MVT::v8i1 ||
1887 LocVT == MVT::v16i1 ||
1888 LocVT == MVT::v32i1) {
1898 if (LocVT == MVT::i32) {
1908 if (LocVT == MVT::i64) {
1918 if (LocVT == MVT::v64i1) {
1929 if (LocVT == MVT::i64) {
1941 if (LocVT == MVT::i64) {
1947 if (LocVT == MVT::f32 ||
1948 LocVT == MVT::f64 ||
1949 LocVT == MVT::f128) {
1961 if (LocVT == MVT::f80) {
1968 if (LocVT == MVT::v16i8 ||
1969 LocVT == MVT::v8i16 ||
1970 LocVT == MVT::v4i32 ||
1971 LocVT == MVT::v2i64 ||
1972 LocVT == MVT::v4f32 ||
1973 LocVT == MVT::v2f64) {
1985 if (LocVT == MVT::v32i8 ||
1986 LocVT == MVT::v16i16 ||
1987 LocVT == MVT::v8i32 ||
1988 LocVT == MVT::v4i64 ||
1989 LocVT == MVT::v8f32 ||
1990 LocVT == MVT::v4f64) {
2002 if (LocVT == MVT::v64i8 ||
2003 LocVT == MVT::v32i16 ||
2004 LocVT == MVT::v16i32 ||
2005 LocVT == MVT::v8i64 ||
2006 LocVT == MVT::v16f32 ||
2007 LocVT == MVT::v8f64) {
2020 if (LocVT == MVT::i32 ||
2021 LocVT == MVT::i64 ||
2022 LocVT == MVT::f32 ||
2023 LocVT == MVT::f64) {
2030 if (LocVT == MVT::i32 ||
2031 LocVT == MVT::f32) {
2037 if (LocVT == MVT::i64 ||
2038 LocVT == MVT::f64) {
2045 if (LocVT == MVT::x86mmx) {
2052 if (LocVT == MVT::x86mmx) {
2058 if (LocVT == MVT::f80 ||
2059 LocVT == MVT::f128) {
2067 if (LocVT == MVT::v16i8 ||
2068 LocVT == MVT::v8i16 ||
2069 LocVT == MVT::v4i32 ||
2070 LocVT == MVT::v2i64 ||
2071 LocVT == MVT::v4f32 ||
2072 LocVT == MVT::v2f64) {
2078 if (LocVT == MVT::v32i8 ||
2079 LocVT == MVT::v16i16 ||
2080 LocVT == MVT::v8i32 ||
2081 LocVT == MVT::v4i64 ||
2082 LocVT == MVT::v8f32 ||
2083 LocVT == MVT::v4f64) {
2089 if (LocVT == MVT::v64i8 ||
2090 LocVT == MVT::v32i16 ||
2091 LocVT == MVT::v16i32 ||
2092 LocVT == MVT::v8i64 ||
2093 LocVT == MVT::v16f32 ||
2094 LocVT == MVT::v8f64) {
2108 if (LocVT == MVT::i32) {
2142 if (LocVT == MVT::i1 ||
2143 LocVT == MVT::v1i1) {
2161 if (LocVT == MVT::i64) {
2176 if (LocVT == MVT::v16i8 ||
2177 LocVT == MVT::v8i16 ||
2178 LocVT == MVT::v4i32 ||
2179 LocVT == MVT::v2i64 ||
2180 LocVT == MVT::v4f32 ||
2181 LocVT == MVT::v2f64) {
2186 if (LocVT == MVT::v32i8 ||
2187 LocVT == MVT::v16i16 ||
2188 LocVT == MVT::v8i32 ||
2189 LocVT == MVT::v4i64 ||
2190 LocVT == MVT::v8f32 ||
2191 LocVT == MVT::v4f64) {
2196 if (LocVT == MVT::v64i8 ||
2197 LocVT == MVT::v32i16 ||
2198 LocVT == MVT::v16i32 ||
2199 LocVT == MVT::v16f32 ||
2200 LocVT == MVT::v8f64 ||
2201 LocVT == MVT::v8i64) {
2206 if (LocVT == MVT::f80) {
2211 if (LocVT == MVT::x86mmx) {
2216 if (LocVT == MVT::i8) {
2229 if (LocVT == MVT::i16) {
2242 if (LocVT == MVT::i32) {
2257 if (LocVT == MVT::i64) {
2272 if (LocVT == MVT::i64) {
2285 if (LocVT == MVT::f32 ||
2286 LocVT == MVT::f64 ||
2287 LocVT == MVT::v16i8 ||
2288 LocVT == MVT::v8i16 ||
2289 LocVT == MVT::v4i32 ||
2290 LocVT == MVT::v2i64 ||
2291 LocVT == MVT::v4f32 ||
2292 LocVT == MVT::v2f64) {
2305 if (LocVT == MVT::i8 ||
2306 LocVT == MVT::i16 ||
2307 LocVT == MVT::i32 ||
2308 LocVT == MVT::i64 ||
2309 LocVT == MVT::f32 ||
2310 LocVT == MVT::f64) {
2336 if (LocVT == MVT::i1 ||
2337 LocVT == MVT::i8 ||
2338 LocVT == MVT::i16 ||
2339 LocVT == MVT::v1i1) {
2349 if (LocVT == MVT::v8i1 ||
2350 LocVT == MVT::v16i1 ||
2351 LocVT == MVT::v32i1) {
2361 if (LocVT == MVT::i32) {
2371 if (LocVT == MVT::i64) {
2381 if (LocVT == MVT::v64i1) {
2392 if (LocVT == MVT::i64) {
2404 if (LocVT == MVT::i64) {
2410 if (LocVT == MVT::f32 ||
2411 LocVT == MVT::f64 ||
2412 LocVT == MVT::f128) {
2424 if (LocVT == MVT::f80) {
2431 if (LocVT == MVT::v16i8 ||
2432 LocVT == MVT::v8i16 ||
2433 LocVT == MVT::v4i32 ||
2434 LocVT == MVT::v2i64 ||
2435 LocVT == MVT::v4f32 ||
2436 LocVT == MVT::v2f64) {
2448 if (LocVT == MVT::v32i8 ||
2449 LocVT == MVT::v16i16 ||
2450 LocVT == MVT::v8i32 ||
2451 LocVT == MVT::v4i64 ||
2452 LocVT == MVT::v8f32 ||
2453 LocVT == MVT::v4f64) {
2465 if (LocVT == MVT::v64i8 ||
2466 LocVT == MVT::v32i16 ||
2467 LocVT == MVT::v16i32 ||
2468 LocVT == MVT::v8i64 ||
2469 LocVT == MVT::v16f32 ||
2470 LocVT == MVT::v8f64) {
2483 if (LocVT == MVT::i32 ||
2484 LocVT == MVT::i64 ||
2485 LocVT == MVT::f32 ||
2486 LocVT == MVT::f64) {
2493 if (LocVT == MVT::i32 ||
2494 LocVT == MVT::f32) {
2500 if (LocVT == MVT::i64 ||
2501 LocVT == MVT::f64) {
2508 if (LocVT == MVT::x86mmx) {
2515 if (LocVT == MVT::x86mmx) {
2521 if (LocVT == MVT::f80 ||
2522 LocVT == MVT::f128) {
2530 if (LocVT == MVT::v16i8 ||
2531 LocVT == MVT::v8i16 ||
2532 LocVT == MVT::v4i32 ||
2533 LocVT == MVT::v2i64 ||
2534 LocVT == MVT::v4f32 ||
2535 LocVT == MVT::v2f64) {
2541 if (LocVT == MVT::v32i8 ||
2542 LocVT == MVT::v16i16 ||
2543 LocVT == MVT::v8i32 ||
2544 LocVT == MVT::v4i64 ||
2545 LocVT == MVT::v8f32 ||
2546 LocVT == MVT::v4f64) {
2552 if (LocVT == MVT::v64i8 ||
2553 LocVT == MVT::v32i16 ||
2554 LocVT == MVT::v16i32 ||
2555 LocVT == MVT::v8i64 ||
2556 LocVT == MVT::v16f32 ||
2557 LocVT == MVT::v8f64) {
2585 if (LocVT == MVT::f32 ||
2586 LocVT == MVT::f64 ||
2587 LocVT == MVT::v4i32 ||
2588 LocVT == MVT::v2i64 ||
2589 LocVT == MVT::v4f32 ||
2590 LocVT == MVT::v2f64) {
2600 if (LocVT == MVT::v8f32 ||
2601 LocVT == MVT::v4f64 ||
2602 LocVT == MVT::v8i32 ||
2603 LocVT == MVT::v4i64) {
2613 if (LocVT == MVT::v16f32 ||
2614 LocVT == MVT::v8f64 ||
2615 LocVT == MVT::v16i32 ||
2616 LocVT == MVT::v8i64) {
2658 if (LocVT == MVT::v1i1) {
2668 if (LocVT == MVT::i1) {
2678 if (LocVT == MVT::i8) {
2688 if (LocVT == MVT::i16) {
2698 if (LocVT == MVT::i32) {
2708 if (LocVT == MVT::i64) {
2718 if (LocVT == MVT::v2i1) {
2728 if (LocVT == MVT::v4i1) {
2738 if (LocVT == MVT::v8i1) {
2748 if (LocVT == MVT::v16i1) {
2758 if (LocVT == MVT::v32i1) {
2768 if (LocVT == MVT::v64i1) {
2778 if (LocVT == MVT::v16i8 ||
2779 LocVT == MVT::v8i16 ||
2780 LocVT == MVT::v4i32 ||
2781 LocVT == MVT::v2i64 ||
2782 LocVT == MVT::v4f32 ||
2783 LocVT == MVT::v2f64) {
2793 if (LocVT == MVT::v32i8 ||
2794 LocVT == MVT::v16i16 ||
2795 LocVT == MVT::v8i32 ||
2796 LocVT == MVT::v4i64 ||
2797 LocVT == MVT::v8f32 ||
2798 LocVT == MVT::v4f64) {
2808 if (LocVT == MVT::v64i8 ||
2809 LocVT == MVT::v32i16 ||
2810 LocVT == MVT::v16i32 ||
2811 LocVT == MVT::v8i64 ||
2812 LocVT == MVT::v16f32 ||
2813 LocVT == MVT::v8f64) {
2823 if (LocVT == MVT::x86mmx) {
2831 if (LocVT == MVT::f80) {
2888 if (LocVT == MVT::f32 ||
2889 LocVT == MVT::f64) {
2901 if (LocVT == MVT::f32 ||
2902 LocVT == MVT::f64) {
2923 if (LocVT == MVT::f32) {
2935 if (LocVT == MVT::f64) {
2947 if (LocVT == MVT::i8) {
2957 if (LocVT == MVT::i16) {
2967 if (LocVT == MVT::i32) {
2988 if (LocVT == MVT::i8 ||
2989 LocVT == MVT::i16) {
2999 if (LocVT == MVT::i32) {
3017 if (LocVT == MVT::i1 ||
3018 LocVT == MVT::v1i1 ||
3019 LocVT == MVT::v8i1) {
3029 if (LocVT == MVT::v16i1) {
3039 if (LocVT == MVT::v32i1) {
3049 if (LocVT == MVT::i8) {
3059 if (LocVT == MVT::i16) {
3069 if (LocVT == MVT::i32) {
3079 if (LocVT == MVT::i64) {
3086 if (LocVT == MVT::v64i1) {
3097 if (LocVT == MVT::i64) {
3106 if (LocVT == MVT::i64) {
3112 if (LocVT == MVT::f80) {
3122 if (LocVT == MVT::f32 ||
3123 LocVT == MVT::f64 ||
3124 LocVT == MVT::f128) {
3136 if (LocVT == MVT::v16i8 ||
3137 LocVT == MVT::v8i16 ||
3138 LocVT == MVT::v4i32 ||
3139 LocVT == MVT::v2i64 ||
3140 LocVT == MVT::v4f32 ||
3141 LocVT == MVT::v2f64) {
3153 if (LocVT == MVT::v32i8 ||
3154 LocVT == MVT::v16i16 ||
3155 LocVT == MVT::v8i32 ||
3156 LocVT == MVT::v4i64 ||
3157 LocVT == MVT::v8f32 ||
3158 LocVT == MVT::v4f64) {
3170 if (LocVT == MVT::v64i8 ||
3171 LocVT == MVT::v32i16 ||
3172 LocVT == MVT::v16i32 ||
3173 LocVT == MVT::v8i64 ||
3174 LocVT == MVT::v16f32 ||
3175 LocVT == MVT::v8f64) {
3195 if (LocVT == MVT::f32 ||
3196 LocVT == MVT::f64 ||
3197 LocVT == MVT::f128) {
3297 if (LocVT == MVT::f32) {
3307 if (LocVT == MVT::f64) {
3317 if (LocVT == MVT::f128) {
3327 if (LocVT == MVT::x86mmx) {
3338 if (LocVT == MVT::i64) {
3357 if (LocVT == MVT::i8 ||
3358 LocVT == MVT::i16 ||
3359 LocVT == MVT::i32) {
3369 if (LocVT == MVT::i64) {
3387 if (LocVT == MVT::i8 ||
3388 LocVT == MVT::i16 ||
3389 LocVT == MVT::i32) {
3399 if (LocVT == MVT::i64) {
3418 if (LocVT == MVT::i64) {
3426 if (LocVT == MVT::v1i1) {
3436 if (LocVT == MVT::i1) {
3446 if (LocVT == MVT::i8) {
3456 if (LocVT == MVT::i16) {
3466 if (LocVT == MVT::i32) {
3476 if (LocVT == MVT::i64) {
3486 if (LocVT == MVT::f32) {
3496 if (LocVT == MVT::f64) {
3506 if (LocVT == MVT::f128) {
3516 if (LocVT == MVT::x86mmx) {
3537 if (LocVT == MVT::f32 ||
3538 LocVT == MVT::f64 ||
3539 LocVT == MVT::f128) {
3560 if (LocVT == MVT::i8 ||
3561 LocVT == MVT::i16 ||
3562 LocVT == MVT::i32) {
3572 if (LocVT == MVT::i64) {
3587 if (LocVT == MVT::i1 ||
3588 LocVT == MVT::v1i1 ||
3589 LocVT == MVT::v8i1) {
3599 if (LocVT == MVT::v16i1) {
3609 if (LocVT == MVT::v32i1) {
3619 if (LocVT == MVT::i8) {
3629 if (LocVT == MVT::i16) {
3639 if (LocVT == MVT::i32) {
3649 if (LocVT == MVT::i64) {
3659 if (LocVT == MVT::v64i1) {
3670 if (LocVT == MVT::i64) {
3682 if (LocVT == MVT::i64) {
3688 if (LocVT == MVT::f80) {
3698 if (LocVT == MVT::f32 ||
3699 LocVT == MVT::f64 ||
3700 LocVT == MVT::f128) {
3712 if (LocVT == MVT::v16i8 ||
3713 LocVT == MVT::v8i16 ||
3714 LocVT == MVT::v4i32 ||
3715 LocVT == MVT::v2i64 ||
3716 LocVT == MVT::v4f32 ||
3717 LocVT == MVT::v2f64) {
3729 if (LocVT == MVT::v32i8 ||
3730 LocVT == MVT::v16i16 ||
3731 LocVT == MVT::v8i32 ||
3732 LocVT == MVT::v4i64 ||
3733 LocVT == MVT::v8f32 ||
3734 LocVT == MVT::v4f64) {
3746 if (LocVT == MVT::v64i8 ||
3747 LocVT == MVT::v32i16 ||
3748 LocVT == MVT::v16i32 ||
3749 LocVT == MVT::v8i64 ||
3750 LocVT == MVT::v16f32 ||
3751 LocVT == MVT::v8f64) {
3771 if (LocVT == MVT::x86mmx) {
3787 if (LocVT == MVT::i1 ||
3788 LocVT == MVT::v1i1 ||
3789 LocVT == MVT::v8i1) {
3799 if (LocVT == MVT::v16i1) {
3809 if (LocVT == MVT::v32i1) {
3819 if (LocVT == MVT::i8) {
3829 if (LocVT == MVT::i16) {
3839 if (LocVT == MVT::i32) {
3849 if (LocVT == MVT::i64) {
3859 if (LocVT == MVT::v64i1) {
3870 if (LocVT == MVT::i64) {
3882 if (LocVT == MVT::i64) {
3888 if (LocVT == MVT::f80) {
3898 if (LocVT == MVT::f32 ||
3899 LocVT == MVT::f64 ||
3900 LocVT == MVT::f128) {
3912 if (LocVT == MVT::v16i8 ||
3913 LocVT == MVT::v8i16 ||
3914 LocVT == MVT::v4i32 ||
3915 LocVT == MVT::v2i64 ||
3916 LocVT == MVT::v4f32 ||
3917 LocVT == MVT::v2f64) {
3929 if (LocVT == MVT::v32i8 ||
3930 LocVT == MVT::v16i16 ||
3931 LocVT == MVT::v8i32 ||
3932 LocVT == MVT::v4i64 ||
3933 LocVT == MVT::v8f32 ||
3934 LocVT == MVT::v4f64) {
3946 if (LocVT == MVT::v64i8 ||
3947 LocVT == MVT::v32i16 ||
3948 LocVT == MVT::v16i32 ||
3949 LocVT == MVT::v8i64 ||
3950 LocVT == MVT::v16f32 ||
3951 LocVT == MVT::v8f64) {
gen/lib/Target/X86/X86GenFastISel.inc14093 if (VT == MVT::i64 && Predicate_i64immSExt32(imm1))
14097 if (VT == MVT::i16 && Predicate_i16immSExt8(imm1))
14101 if (VT == MVT::i32 && Predicate_i32immSExt8(imm1))
14105 if (VT == MVT::i64 && Predicate_i64immSExt8(imm1))
gen/lib/Target/XCore/XCoreGenCallingConv.inc 21 if (LocVT == MVT::i8 ||
22 LocVT == MVT::i16) {
39 if (LocVT == MVT::i32) {
49 if (LocVT == MVT::i32) {
63 if (LocVT == MVT::i32) {
73 if (LocVT == MVT::i32) {
include/llvm/ADT/SmallSet.h 240 if (*I == V)
include/llvm/CodeGen/CostTable.h 34 return ISD == Entry.ISD && Ty == Entry.Type;
57 return ISD == Entry.ISD && Src == Entry.Src && Dst == Entry.Dst;
57 return ISD == Entry.ISD && Src == Entry.Src && Dst == Entry.Dst;
include/llvm/CodeGen/TargetLowering.h 419 getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
include/llvm/CodeGen/TargetRegisterInfo.h 290 if (MVT(*I) == T)
include/llvm/CodeGen/ValueTypes.h 207 return (V==MVT::iAny || V==MVT::fAny || V==MVT::vAny || V==MVT::iPTRAny);
207 return (V==MVT::iAny || V==MVT::fAny || V==MVT::vAny || V==MVT::iPTRAny);
207 return (V==MVT::iAny || V==MVT::fAny || V==MVT::vAny || V==MVT::iPTRAny);
207 return (V==MVT::iAny || V==MVT::fAny || V==MVT::vAny || V==MVT::iPTRAny);
lib/CodeGen/GlobalISel/CallLowering.cpp 365 unsigned Size = VT == MVT::iPTR ? DL.getPointerSize()
lib/CodeGen/SelectionDAG/FastISel.cpp 374 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
374 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
374 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
1549 if (SrcVT == DstVT) {
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 128 if (VT == MVT::Other || VT == MVT::Glue)
128 if (VT == MVT::Other || VT == MVT::Glue)
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3148 if ((SVT == MVT::f64 || SVT == MVT::f80) &&
3148 if ((SVT == MVT::f64 || SVT == MVT::f80) &&
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 144 CN->getValueType(0).getSimpleVT() == llvm::MVT::ppcf128) {
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp 222 if (VT == MVT::Glue)
224 else if (VT == MVT::Other)
229 if (VT == MVT::Glue)
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 319 if (VT == MVT::Untyped) {
1155 if (VT == MVT::Glue) {
1158 } else if (VT == MVT::Other)
1163 if (VT == MVT::Glue && !TII->canCopyGluedNodeDuringSchedule(N)) {
2309 if (VT == MVT::Glue || VT == MVT::Other)
2309 if (VT == MVT::Glue || VT == MVT::Other)
2891 if (VT == MVT::Glue || VT == MVT::Other)
2891 if (VT == MVT::Glue || VT == MVT::Other)
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 5336 if (VT.getSimpleVT() == N1.getSimpleValueType())
5544 if (VT.getSimpleVT() == N2.getSimpleValueType())
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 266 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
387 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
538 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
543 if (PartVT == MVT::x86mmx)
552 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
557 if (PartVT == MVT::x86mmx)
720 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
7329 if (LoadVT == MVT::INVALID_SIMPLE_VALUE_TYPE)
7809 if (OpInfo.ConstraintVT == MatchingOpInfo.ConstraintVT)
7951 if (OpInfo.ConstraintVT == MVT::Other)
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 3114 if (CaseVT == MVT::iPTR)
3118 if (CurNodeVT == CaseVT)
lib/CodeGen/TargetLoweringBase.cpp 940 if (LargerVector == MVT())
1304 if (SVT.getVectorElementType() == EltVT
1340 if (NVT == VT) {
lib/CodeGen/TargetRegisterInfo.cpp 198 if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) &&
lib/Target/AArch64/AArch64FastISel.cpp 388 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass
390 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
407 bool Is64Bit = (VT == MVT::f64);
535 assert(VT == MVT::i64 && "Expected 64-bit pointers");
559 bool Is64Bit = (VT == MVT::f64);
989 if (VT == MVT::f128)
1010 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
1010 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
1010 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
1333 bool Is64Bit = RetVT == MVT::i64;
1375 bool Is64Bit = RetVT == MVT::i64;
1420 bool Is64Bit = RetVT == MVT::i64;
1462 bool Is64Bit = RetVT == MVT::i64;
1536 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDri : AArch64::FCMPSri;
1547 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDrr : AArch64::FCMPSrr;
1685 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1731 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1774 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1861 bool IsRet64Bit = RetVT == MVT::i64;
1902 if (VT == MVT::i1) {
1910 if (WantZExt && RetVT == MVT::i64 && VT <= MVT::i32) {
2049 if (RetVT == MVT::i64 && VT <= MVT::i32) {
2208 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
2212 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
2354 if (VT == MVT::i1)
2888 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
2890 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
2893 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
2895 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
2898 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);
2910 if (DestVT == MVT::f16)
2913 assert((DestVT == MVT::f32 || DestVT == MVT::f64) &&
2913 assert((DestVT == MVT::f32 || DestVT == MVT::f64) &&
2935 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;
2937 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;
2940 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;
2942 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;
3031 } else if (VT == MVT::i64) {
3034 } else if (VT == MVT::f16) {
3037 } else if (VT == MVT::f32) {
3040 } else if ((VT == MVT::f64) || VT.is64BitVector()) {
3242 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
3242 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
3242 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
3584 bool Is64Bit = RetVT == MVT::f64;
3755 if (VT == MVT::i32) {
3766 assert(VT == MVT::i64 && "Unexpected value type.");
3790 if (VT == MVT::i32) {
3798 assert(VT == MVT::i64 && "Unexpected value type.");
3907 if (RVVT == MVT::f128)
3973 if (SrcVT == MVT::i64) {
4007 assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
4007 assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
4007 assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
4008 DestVT == MVT::i64) &&
4011 if (DestVT == MVT::i8 || DestVT == MVT::i16)
4011 if (DestVT == MVT::i8 || DestVT == MVT::i16)
4017 if (DestVT == MVT::i64) {
4030 if (DestVT == MVT::i64) {
4054 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4093 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4110 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
4110 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
4110 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
4111 SrcVT == MVT::i32 || SrcVT == MVT::i64) &&
4111 SrcVT == MVT::i32 || SrcVT == MVT::i64) &&
4113 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4113 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4113 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4114 RetVT == MVT::i64) && "Unexpected return value type.");
4116 bool Is64Bit = (RetVT == MVT::i64);
4125 if (RetVT == SrcVT) {
4172 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4199 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4217 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
4217 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
4217 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
4218 SrcVT == MVT::i32 || SrcVT == MVT::i64) &&
4218 SrcVT == MVT::i32 || SrcVT == MVT::i64) &&
4220 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4220 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4220 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4221 RetVT == MVT::i64) && "Unexpected return value type.");
4223 bool Is64Bit = (RetVT == MVT::i64);
4232 if (RetVT == SrcVT) {
4293 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4320 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4338 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
4338 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
4338 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
4339 SrcVT == MVT::i32 || SrcVT == MVT::i64) &&
4339 SrcVT == MVT::i32 || SrcVT == MVT::i64) &&
4341 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4341 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4341 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4342 RetVT == MVT::i64) && "Unexpected return value type.");
4344 bool Is64Bit = (RetVT == MVT::i64);
4353 if (RetVT == SrcVT) {
4402 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4438 if (DestVT == MVT::i64)
4445 if (DestVT == MVT::i64)
4452 assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");
4459 if (DestVT == MVT::i8 || DestVT == MVT::i16)
4459 if (DestVT == MVT::i8 || DestVT == MVT::i16)
4461 else if (DestVT == MVT::i64) {
4472 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4602 if (RetVT == MVT::i64 && SrcVT != MVT::i64) {
4642 bool Is64bit = (DestVT == MVT::i64);
4665 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4849 if (RetVT == MVT::f32 && SrcVT == MVT::i32)
4849 if (RetVT == MVT::f32 && SrcVT == MVT::i32)
4851 else if (RetVT == MVT::f64 && SrcVT == MVT::i64)
4851 else if (RetVT == MVT::f64 && SrcVT == MVT::i64)
4853 else if (RetVT == MVT::i32 && SrcVT == MVT::f32)
4853 else if (RetVT == MVT::i32 && SrcVT == MVT::f32)
4855 else if (RetVT == MVT::i64 && SrcVT == MVT::f64)
4855 else if (RetVT == MVT::i64 && SrcVT == MVT::f64)
4957 if (VT == MVT::i64) {
4972 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
5099 if (VT == MVT::i32) {
5103 } else if (VT == MVT::i64) {
5133 .addDef(VT == MVT::i32 ? AArch64::WZR : AArch64::XZR)
lib/Target/AArch64/AArch64ISelLowering.cpp 759 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32) {
759 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32) {
759 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32) {
827 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
827 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
827 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
1104 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
1104 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
1108 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
1108 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
3168 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
3168 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
3170 else if (ActualMVT == MVT::i16)
3499 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
3790 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
3790 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
3792 else if (ActualMVT == MVT::i16)
3887 assert(VA.getValVT() == MVT::i32 && "only expect 32 -> 64 upper bits");
3909 Outs[0].VT == MVT::i64) {
3910 assert(VA.getLocVT() == MVT::i64 &&
3912 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
3999 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
3999 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
4000 VA.getValVT() == MVT::i16)
4206 assert(VA.getValVT() == MVT::i32 && "only expect 32 -> 64 upper bits");
9614 if (ResTy == MVT::v4i64 && DCI.isBeforeLegalizeOps())
9687 if (ResTy == MVT::v4i64 && DCI.isBeforeLegalizeOps())
12115 if (VT == MVT::v1i8 || VT == MVT::v1i16 || VT == MVT::v1i32 ||
12115 if (VT == MVT::v1i8 || VT == MVT::v1i16 || VT == MVT::v1i32 ||
12115 if (VT == MVT::v1i8 || VT == MVT::v1i16 || VT == MVT::v1i32 ||
12116 VT == MVT::v1f32)
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 2024 if (VT == MVT::i32)
2027 if (VT == MVT::i64) {
2141 bool Is32 = (VT == MVT::i32);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 115 if (VT == MVT::i64)
549 return N->getNumOperands() > 2 || VT == MVT::f64;
2593 assert(N0.getSimpleValueType() == MVT::f64);
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 1547 if (type == MVT::f64 || type == MVT::i64) { // Expected 64-bit operand
1547 if (type == MVT::f64 || type == MVT::i64) { // Expected 64-bit operand
1569 if (type == MVT::f64 || type == MVT::i64) { // Expected 64-bit operand
1569 if (type == MVT::f64 || type == MVT::i64) { // Expected 64-bit operand
1598 if (type == MVT::f64 && hasFPModifiers()) {
1615 if (type == MVT::f64) { // Expected 64-bit fp operand
1620 if (type == MVT::i64) { // Expected 64-bit int operand
1629 MVT ExpectedType = (type == MVT::v2f16)? MVT::f16 :
1630 (type == MVT::v2i16)? MVT::i16 : type;
lib/Target/AMDGPU/SIISelLowering.cpp 5373 if (StoreVT.getScalarType() == MVT::f16) {
5386 if (LoadVT.getScalarType() == MVT::f16) {
5444 if (((VAddrScalarVT == MVT::f16) || (VAddrScalarVT == MVT::i16)) &&
5444 if (((VAddrScalarVT == MVT::f16) || (VAddrScalarVT == MVT::i16)) &&
5447 const MVT VectorVT = VAddrScalarVT == MVT::f16 ? MVT::v2f16 : MVT::v2i16;
5665 assert((LoadVT.getScalarType() == MVT::i32 ||
5666 LoadVT.getScalarType() == MVT::f32) &&
lib/Target/ARM/ARMCallLowering.cpp 146 assert(VA.getValVT() == MVT::f64 && "Unsupported type");
150 assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
370 assert(VA.getValVT() == MVT::f64 && "Unsupported type");
374 assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
lib/Target/ARM/ARMCallingConv.cpp 57 if (LocVT == MVT::v2f64 &&
111 if (LocVT == MVT::v2f64 &&
143 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
181 assert(PendingMembers[0].getLocVT() == LocVT);
244 if (LocVT == MVT::i32 && State.getNextStackOffset() == 0) {
lib/Target/ARM/ARMFastISel.cpp 399 if (VT == MVT::f64) return 0;
409 if (VT == MVT::i64) return 0;
423 bool is64bit = VT == MVT::f64;
483 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
706 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
706 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
706 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
1371 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1371 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1371 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1372 SrcVT == MVT::i1) {
1386 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1386 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1558 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1558 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1633 assert(VT == MVT::i32 && "Expecting an i32.");
1705 if (VT == MVT::i8)
1707 else if (VT == MVT::i16)
1709 else if (VT == MVT::i32)
1711 else if (VT == MVT::i64)
1713 else if (VT == MVT::i128)
1734 if (VT == MVT::i8)
1736 else if (VT == MVT::i16)
1738 else if (VT == MVT::i32)
1740 else if (VT == MVT::i64)
1742 else if (VT == MVT::i128)
1809 bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1809 bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1998 assert(VA.getLocVT() == MVT::f64 &&
2050 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2071 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2071 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2071 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2146 assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2929 MVT((MVT::SimpleValueType)FLE.ExpectedVT) == VT) {
lib/Target/ARM/ARMISelLowering.cpp 165 if (ElemTy == MVT::i32) {
1699 if (VT == MVT::v4i64)
1701 if (VT == MVT::v8i64)
1943 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1965 if (VA.getLocVT() == MVT::v2f64) {
2158 if (VA.getLocVT() == MVT::v2f64) {
2183 Outs[0].VT == MVT::i32) {
2184 assert(VA.getLocVT() == MVT::i32 &&
2186 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
2787 if (VA.getLocVT() == MVT::v2f64) {
4026 if (VA.getLocVT() == MVT::v2f64) {
7244 assert(FVT == MVT::f32 || FVT == MVT::f16);
7244 assert(FVT == MVT::f32 || FVT == MVT::f16);
7245 MVT IVT = (FVT == MVT::f32) ? MVT::i32 : MVT::i16;
9107 SDValue Callee = DAG.getExternalSymbol(Ty == MVT::f32 ? "powf" : "pow",
15694 if (VT == MVT::Other)
15696 if (VT == MVT::f32)
15704 if (VT == MVT::Other)
15706 if (VT == MVT::f32)
15714 if (VT == MVT::Other)
15716 if (VT == MVT::f32 || VT == MVT::i32)
15716 if (VT == MVT::f32 || VT == MVT::i32)
15978 Op->getSimpleValueType(0) == MVT::i32) {
lib/Target/ARM/ARMTargetTransformInfo.cpp 708 if (LT.second == MVT::v2i64 &&
lib/Target/AVR/AVRISelDAGToDAG.cpp 110 if (isUInt<6>(RHSC) && (VT == MVT::i8 || VT == MVT::i16)) {
110 if (isUInt<6>(RHSC) && (VT == MVT::i8 || VT == MVT::i16)) {
475 assert(Type == MVT::i8 && "unexpected value type");
lib/Target/AVR/AVRISelLowering.cpp 979 const MCPhysReg *RegList = (LocVT == MVT::i16) ? RegList16 : RegList8;
1875 if (VT == MVT::i8)
1878 assert(VT == MVT::i16 && "inline asm constraint too large");
1963 if (Ty.getSimpleVT() == MVT::i8) {
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 1170 if (!UVT.isSimple() || !UVT.isInteger() || UVT.getSimpleVT() == MVT::i1)
lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp 1365 assert(ElemTy == MVT::i8);
2008 assert(ResTy.isVector() && ResTy.getVectorElementType() == MVT::i8);
lib/Target/Hexagon/HexagonISelLowering.cpp 279 if (RVLocs[i].getValVT() == MVT::i1) {
745 if (VA.getValVT() == MVT::i1) {
818 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
818 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
857 if (OpTy == MVT::i8 || OpTy == MVT::i16) {
857 if (OpTy == MVT::i8 || OpTy == MVT::i16) {
876 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
876 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
1448 if (TargetVT == VT)
1847 return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32;
1847 return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32;
1886 if (ElemTy == MVT::i1 && VecLen == 2*HwLen)
1891 if (ElemTy == MVT::i1)
2083 if (ResTy == MVT::v8i1) {
2142 if (ElemTy == MVT::i16) {
2154 if (ElemTy == MVT::i8) {
2226 if (ElemTy == MVT::i16) {
2247 uint64_t Mask = (ElemTy == MVT::i8) ? 0xFFull
2248 : (ElemTy == MVT::i16) ? 0xFFFFull : 0xFFFFFFFFull;
2257 SDValue L = (ElemTy == MVT::i32)
2260 SDValue H = (ElemTy == MVT::i32)
2272 VecTy.getVectorElementType() == ValTy.getVectorElementType());
2309 assert(ty(IdxV) == MVT::i32);
2370 if (VecTy.getVectorElementType() == MVT::i1) {
2372 assert(ValTy.getVectorElementType() == MVT::i1);
2481 if (VecTy == MVT::v8i1 || VecTy == MVT::v4i1 || VecTy == MVT::v2i1) {
2481 if (VecTy == MVT::v8i1 || VecTy == MVT::v4i1 || VecTy == MVT::v2i1) {
2481 if (VecTy == MVT::v8i1 || VecTy == MVT::v4i1 || VecTy == MVT::v2i1) {
2533 if (ElemTy == MVT::i1) {
2534 assert(VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1);
2534 assert(VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1);
2534 assert(VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1);
3209 if (VT.getVectorElementType() == MVT::i1)
lib/Target/Hexagon/HexagonISelLowering.h 388 if (Ty.isVector() && Ty.getVectorElementType() == ElemTy)
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 212 assert(Tys.first.getVectorElementType() == Tys.second.getVectorElementType());
245 if (ty(Vec).getVectorElementType() == ElemTy)
316 assert(OpTy == ty(Op1));
319 if (ElemTy == MVT::i8)
533 assert(PredTy == MVT::v2i1 || PredTy == MVT::v4i1 || PredTy == MVT::v8i1);
533 assert(PredTy == MVT::v2i1 || PredTy == MVT::v4i1 || PredTy == MVT::v8i1);
533 assert(PredTy == MVT::v2i1 || PredTy == MVT::v4i1 || PredTy == MVT::v8i1);
668 if (ElemTy == MVT::i32)
684 assert(ResTy == MVT::i1);
723 if (ElemTy == MVT::i32)
782 if (VecTy == ResTy)
1029 if (VecTy.getVectorElementType() == MVT::i1)
1088 assert(VecTy.getVectorElementType() == MVT::i1);
1141 if (ElemTy == MVT::i1)
1155 if (ElemTy == MVT::i1)
1174 if (ElemTy == MVT::i1)
1191 if (ElemTy == MVT::i1)
1206 if (ElemTy == MVT::i1 && Subtarget.isHVXVectorType(ResTy))
1216 if (ElemTy == MVT::i1 && Subtarget.isHVXVectorType(ResTy))
1226 if (ElemTy == MVT::i1 && Subtarget.isHVXVectorType(ResTy))
1238 assert(ResTy == ty(InpV));
1284 unsigned MpyOpc = ElemTy == MVT::i8 ? Hexagon::V6_vmpybv
1333 if (ElemTy == MVT::i8 || ElemTy == MVT::i16) {
1333 if (ElemTy == MVT::i8 || ElemTy == MVT::i16) {
1341 unsigned MpyOpc = ElemTy == MVT::i8
1356 assert(ElemTy == MVT::i32);
lib/Target/Hexagon/HexagonInstrInfo.cpp 1986 if (VT == MVT::i1) {
1988 } else if (VT == MVT::i32 || VT == MVT::f32) {
1988 } else if (VT == MVT::i32 || VT == MVT::f32) {
1990 } else if (VT == MVT::i64 || VT == MVT::f64) {
1990 } else if (VT == MVT::i64 || VT == MVT::f64) {
lib/Target/Hexagon/HexagonSubtarget.h 234 if (!IncludeBool && ElemTy == MVT::i1)
241 if (IncludeBool && ElemTy == MVT::i1) {
256 return llvm::any_of(ElemTypes, [ElemTy] (MVT T) { return ElemTy == T; });
lib/Target/Lanai/LanaiISelLowering.cpp 380 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
380 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
lib/Target/MSP430/MSP430ISelDAGToDAG.cpp 363 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
lib/Target/MSP430/MSP430ISelLowering.cpp 386 if (VT == MVT::i8)
489 if (LocVT == MVT::i8) {
lib/Target/Mips/MipsFastISel.cpp 393 if (VT == MVT::f32) {
399 } else if (VT == MVT::f64) {
617 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
617 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
617 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
629 if (VT == MVT::i8 || VT == MVT::i16)
629 if (VT == MVT::i8 || VT == MVT::i16)
1036 } else if (VT == MVT::f32) {
1039 } else if (VT == MVT::f64) {
1129 unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32;
1162 if (ArgVT == MVT::f32) {
1164 } else if (ArgVT == MVT::f64) {
1171 if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1171 if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1172 if (ArgVT == MVT::f32) {
1174 } else if (ArgVT == MVT::f64) {
1182 if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1182 if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1182 if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1183 (ArgVT == MVT::i8)) &&
1297 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1297 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1297 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1532 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1532 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1532 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1606 if (VT == MVT::i16) {
1625 } else if (VT == MVT::i32) {
1744 if (RVVT == MVT::f128)
1748 if (RVVT == MVT::f64 && UnsupportedFPMode) {
2102 if (VMVT == MVT::i1)
2105 if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
2105 if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
lib/Target/Mips/MipsISelLowering.cpp 2757 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2757 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2757 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2769 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2769 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2787 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2791 if (ValVT == MVT::i32 && isVectorFloat) {
2807 } else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2807 } else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2814 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2824 if (ValVT == MVT::f32) {
3157 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3157 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3158 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
3158 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
3159 (ValVT == MVT::i64 && LocVT == MVT::f64))
3159 (ValVT == MVT::i64 && LocVT == MVT::f64))
3161 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3161 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3536 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3537 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3538 (RegVT == MVT::f64 && ValVT == MVT::i64))
3540 else if (ABI.IsO32() && RegVT == MVT::i32 &&
3927 if (VT == MVT::Other)
3939 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
3942 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
3961 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3961 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3961 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3966 if (VT == MVT::i64 && !Subtarget.isGP64bit())
3968 if (VT == MVT::i64 && Subtarget.isGP64bit())
3973 if (VT == MVT::v16i8)
3975 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
3975 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
3977 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
3977 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
3979 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
3979 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
3981 else if (VT == MVT::f32)
3983 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
3990 if (VT == MVT::i32)
3992 if (VT == MVT::i64)
3998 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
3998 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
3998 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 918 if (ResTy == MVT::i32) {
lib/Target/Mips/MipsSEISelLowering.cpp 309 if (VT == MVT::Untyped)
1239 if (Src == MVT::i64 && Dest == MVT::f64) {
1239 if (Src == MVT::i64 && Dest == MVT::f64) {
1248 if (Src == MVT::f64 && Dest == MVT::i64) {
1248 if (Src == MVT::f64 && Dest == MVT::i64) {
lib/Target/NVPTX/NVPTXISelLowering.cpp 1193 if (VT.getVectorNumElements() != 1 && VT.getScalarType() == MVT::i1)
1195 if (VT == MVT::v2f16)
1335 (getValueType(DL, Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
lib/Target/PowerPC/PPCFastISel.cpp 293 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
293 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
293 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
471 (VT == MVT::f64 ? (HasSPE ? &PPC::SPERCRegClass : &PPC::F8RCRegClass) :
472 (VT == MVT::f32 ? (HasSPE ? &PPC::GPRCRegClass : &PPC::F4RCRegClass) :
473 (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
830 if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits())
844 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
844 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
844 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
845 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
845 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
1023 if (SrcVT == MVT::i32) {
1043 if (SrcVT == MVT::i32) {
1091 if (DstVT == MVT::f32)
1114 if (DstVT == MVT::f32 && !PPCSubTarget->hasFPCVT())
1118 if (SrcVT == MVT::i8 || SrcVT == MVT::i16) {
1118 if (SrcVT == MVT::i8 || SrcVT == MVT::i16) {
1136 if (DstVT == MVT::f32)
1170 if (VT == MVT::i32)
1199 if (DstVT == MVT::i64 && !IsSigned &&
1237 if (DstVT == MVT::i32)
1243 if (DstVT == MVT::i32)
1398 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64 || ArgVT == MVT::i1 ||
1444 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1456 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1473 if (ArgVT == MVT::f32 || ArgVT == MVT::f64) {
1473 if (ArgVT == MVT::f32 || ArgVT == MVT::f64) {
1514 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
1514 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
1514 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
1520 if (RetVT == CopyVT) {
1525 } else if (CopyVT == MVT::f64) {
1534 } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) {
1534 } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) {
1534 } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) {
1576 else if (RetVT == MVT::i1 && PPCSubTarget->useCRBits())
1766 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1775 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1814 if (SrcVT == MVT::i8)
1815 Opc = (DestVT == MVT::i32) ? PPC::EXTSB : PPC::EXTSB8_32_64;
1816 else if (SrcVT == MVT::i16)
1817 Opc = (DestVT == MVT::i32) ? PPC::EXTSH : PPC::EXTSH8_32_64;
1819 assert(DestVT == MVT::i64 && "Signed extend from i32 to i32??");
1826 } else if (DestVT == MVT::i32) {
1828 if (SrcVT == MVT::i8)
1831 assert(SrcVT == MVT::i16 && "Unsigned extend from i32 to i32??");
1841 if (SrcVT == MVT::i8)
1843 else if (SrcVT == MVT::i16)
1924 (DestVT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
2005 RC = ((VT == MVT::f32) ? &PPC::GPRCRegClass : &PPC::SPERCRegClass);
2007 RC = ((VT == MVT::f32) ? &PPC::F4RCRegClass : &PPC::F8RCRegClass);
2014 MachineMemOperand::MOLoad, (VT == MVT::f32) ? 4 : 8, Align);
2019 Opc = ((VT == MVT::f32) ? PPC::SPELWZ : PPC::EVLDD);
2021 Opc = ((VT == MVT::f32) ? PPC::LFS : PPC::LFD);
2059 assert(VT == MVT::i64 && "Non-address!");
2203 if (VT == MVT::i1 && PPCSubTarget->useCRBits()) {
2215 ((VT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass);
2223 unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
2231 if (VT == MVT::i64)
2233 else if (VT == MVT::i32)
2310 if ((VT == MVT::i8 && MB <= 56) ||
2311 (VT == MVT::i16 && MB <= 48) ||
2312 (VT == MVT::i32 && MB <= 32))
2321 if ((VT == MVT::i8 && MB <= 24) ||
2322 (VT == MVT::i16 && MB <= 16))
2385 if (VT == MVT::i1 && PPCSubTarget->useCRBits()) {
2396 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2398 if (VT == MVT::i64)
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 439 if (PPCLowering->getPointerTy(CurDAG->getDataLayout()) == MVT::i32) {
3926 if (VecVT == MVT::v4f32)
3928 else if (VecVT == MVT::v2f64)
3933 if (VecVT == MVT::v4f32)
3935 else if (VecVT == MVT::v2f64)
3940 if (VecVT == MVT::v4f32)
3942 else if (VecVT == MVT::v2f64)
3970 if (VecVT == MVT::v16i8)
3972 else if (VecVT == MVT::v8i16)
3974 else if (VecVT == MVT::v4i32)
3976 else if (VecVT == MVT::v2i64)
3980 if (VecVT == MVT::v16i8)
3982 else if (VecVT == MVT::v8i16)
3984 else if (VecVT == MVT::v4i32)
3986 else if (VecVT == MVT::v2i64)
3990 if (VecVT == MVT::v16i8)
3992 else if (VecVT == MVT::v8i16)
3994 else if (VecVT == MVT::v4i32)
3996 else if (VecVT == MVT::v2i64)
4220 assert((N->getSimpleValueType(0) == MVT::i64 ||
4221 N->getSimpleValueType(0) == MVT::i32) &&
4836 N, N->getSimpleValueType(0) == MVT::i64 ? PPC::SETB8 : PPC::SETB,
lib/Target/PowerPC/PPCISelLowering.cpp 3532 if (VA.getLocVT() == MVT::f64 && Subtarget.hasSPE()) {
5173 if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) {
6711 if (ValVT == MVT::f128)
6923 if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) {
10629 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
10629 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
10761 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
10761 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
10765 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
10768 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
10769 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
10771 (PVT == MVT::i64)
10788 if (PVT == MVT::i64) {
10800 if (PVT == MVT::i64) {
10812 if (PVT == MVT::i64) {
10824 if (PVT == MVT::i64) {
10836 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
10846 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
10847 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
13495 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
13495 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
13496 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
13496 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
13510 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
13510 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
13511 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
13511 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
13828 if ((V1.getSimpleValueType() == MVT::v4i32 ||
13829 V1.getSimpleValueType() == MVT::v8i16 ||
13830 V1.getSimpleValueType() == MVT::v16i8) &&
13831 V1.getSimpleValueType() == V2.getSimpleValueType()) {
14313 if (VT == MVT::i64 && Subtarget.isPPC64())
14317 if (VT == MVT::i64 && Subtarget.isPPC64())
14326 if (VT == MVT::f32 || VT == MVT::i32)
14326 if (VT == MVT::f32 || VT == MVT::i32)
14328 if (VT == MVT::f64 || VT == MVT::i64)
14328 if (VT == MVT::f64 || VT == MVT::i64)
14331 if (VT == MVT::f32 || VT == MVT::i32)
14331 if (VT == MVT::f32 || VT == MVT::i32)
14333 if (VT == MVT::f64 || VT == MVT::i64)
14333 if (VT == MVT::f64 || VT == MVT::i64)
14335 if (VT == MVT::v4f64 && Subtarget.hasQPX())
14337 if (VT == MVT::v4f32 && Subtarget.hasQPX())
14342 if (VT == MVT::v4f64 && Subtarget.hasQPX())
14344 if (VT == MVT::v4f32 && Subtarget.hasQPX())
14360 if (VT == MVT::f32 && Subtarget.hasP8Vector())
14375 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
lib/Target/PowerPC/PPCTargetTransformInfo.cpp 848 (LT.second == MVT::v16i8 || LT.second == MVT::v8i16 ||
848 (LT.second == MVT::v16i8 || LT.second == MVT::v8i16 ||
849 LT.second == MVT::v4i32 || LT.second == MVT::v4f32);
849 LT.second == MVT::v4i32 || LT.second == MVT::v4f32);
851 (LT.second == MVT::v2f64 || LT.second == MVT::v2i64);
851 (LT.second == MVT::v2f64 || LT.second == MVT::v2i64);
853 (LT.second == MVT::v4f64 || LT.second == MVT::v4f32);
853 (LT.second == MVT::v4f64 || LT.second == MVT::v4f32);
lib/Target/RISCV/RISCVISelDAGToDAG.cpp 69 RISCVMatInt::generateInstSeq(Imm, XLenVT == MVT::i64, Seq);
123 if (XLenVT == MVT::i64) {
lib/Target/RISCV/RISCVISelLowering.cpp 626 if (Op.getSimpleValueType() == XLenVT && CondV.getOpcode() == ISD::SETCC &&
627 CondV.getOperand(0).getSimpleValueType() == XLenVT) {
1492 if (UseGPRForF32 && ValVT == MVT::f32) {
1495 } else if (UseGPRForF64 && XLen == 64 && ValVT == MVT::f64) {
1525 if (UseGPRForF64 && XLen == 32 && ValVT == MVT::f64) {
1575 if (ValVT == MVT::f32 && !UseGPRForF32)
1577 else if (ValVT == MVT::f64 && !UseGPRForF64)
1601 assert((!UseGPRForF32 || !UseGPRForF64 || LocVT == XLenVT) &&
1610 if (ValVT == MVT::f32 || ValVT == MVT::f64) {
1610 if (ValVT == MVT::f32 || ValVT == MVT::f64) {
1675 if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) {
1675 if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) {
1730 if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) {
1730 if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) {
1772 assert(VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64 &&
1772 assert(VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64 &&
1813 if (LocVT == MVT::i32 || LocVT == MVT::i64) {
1813 if (LocVT == MVT::i32 || LocVT == MVT::i64) {
1825 if (LocVT == MVT::f32) {
1837 if (LocVT == MVT::f64) {
1849 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
1849 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
1855 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
1855 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
1914 if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64)
1914 if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64)
2163 VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;
2163 VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;
2343 if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) {
2343 if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) {
2405 if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) {
2405 if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) {
2565 if (Subtarget.hasStdExtF() && VT == MVT::f32)
2567 if (Subtarget.hasStdExtD() && VT == MVT::f64)
lib/Target/Sparc/SparcISelLowering.cpp 109 assert((LocVT == MVT::f32 || LocVT == MVT::f128
109 assert((LocVT == MVT::f32 || LocVT == MVT::f128
114 unsigned size = (LocVT == MVT::f128) ? 16 : 8;
115 unsigned alignment = (LocVT == MVT::f128) ? 16 : 8;
119 if (LocVT == MVT::i64 && Offset < 6*8)
122 else if (LocVT == MVT::f64 && Offset < 16*8)
125 else if (LocVT == MVT::f32 && Offset < 16*8)
128 else if (LocVT == MVT::f128 && Offset < 16*8)
141 if (LocVT == MVT::f32)
157 if (LocVT == MVT::f32 && Offset < 16*8) {
164 if (LocVT == MVT::i32 && Offset < 6*8) {
240 assert(VA.getLocVT() == MVT::v2i32);
339 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
418 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
418 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
451 if (VA.getLocVT() == MVT::f32)
468 assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32);
468 assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32);
510 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
510 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
512 } else if (VA.getValVT() == MVT::f128) {
605 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
837 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
837 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
852 if (VA.getLocVT() == MVT::f64) {
989 if (RVLocs[i].getLocVT() == MVT::v2i32) {
1063 unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1064 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16;
1071 if (ValTy == MVT::f64)
1076 assert(ValTy == MVT::f128 && "Unexpected type!");
1166 if (VA.needsCustom() && VA.getValVT() == MVT::f128
1167 && VA.getLocVT() == MVT::i128) {
1194 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1295 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CS)
1321 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
3080 if (isa<ConstantFPSDNode>(Src) && N->getSimpleValueType(0) == MVT::v2i32 &&
3081 Src.getSimpleValueType() == MVT::f64)
3261 if (VT == MVT::v2i32)
3268 if (VT == MVT::f32 || VT == MVT::i32)
3268 if (VT == MVT::f32 || VT == MVT::i32)
3270 else if (VT == MVT::f64 || VT == MVT::i64)
3270 else if (VT == MVT::f64 || VT == MVT::i64)
3272 else if (VT == MVT::f128)
3277 if (VT == MVT::f32 || VT == MVT::i32)
3277 if (VT == MVT::f32 || VT == MVT::i32)
3279 else if (VT == MVT::f64 || VT == MVT::i64 )
3279 else if (VT == MVT::f64 || VT == MVT::i64 )
3281 else if (VT == MVT::f128)
3311 if (VT == MVT::f32 || VT == MVT::Other) {
3311 if (VT == MVT::f32 || VT == MVT::Other) {
3313 } else if (VT == MVT::f64 && (intVal % 2 == 0)) {
3315 } else if (VT == MVT::f128 && (intVal % 4 == 0)) {
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 1157 if (VCI.VecVT == VT.getSimpleVT())
lib/Target/SystemZ/SystemZISelLowering.cpp 1078 if (VT == MVT::i64)
1080 else if (VT == MVT::i128)
1085 if (VT == MVT::i64)
1087 else if (VT == MVT::i128)
1095 if (VT == MVT::f64)
1097 else if (VT == MVT::f128)
1103 if (VT == MVT::f32)
1105 if (VT == MVT::f64)
1118 if (VT == MVT::i32)
1121 if (VT == MVT::i128)
1128 if (VT == MVT::f32)
1131 if (VT == MVT::f128)
1138 if (VT == MVT::f32)
1141 if (VT == MVT::f64)
1257 assert(VA.getLocVT() == MVT::i64);
1281 assert(VA.getLocVT() == MVT::i64);
1368 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
1368 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
1541 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
1541 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
7805 if (VT == MVT::Untyped)
lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp 151 assert(PtrVT == MVT::i32 && "only wasm32 is supported for now");
173 assert(PtrVT == MVT::i32 && "only wasm32 is supported for now");
183 assert(PtrVT == MVT::i32 && "only wasm32 is supported for now");
199 assert(PtrVT == MVT::i32 && "only wasm32 is supported for now");
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 556 return (ExtT == MVT::v8i16 && MemT == MVT::v8i8) ||
556 return (ExtT == MVT::v8i16 && MemT == MVT::v8i8) ||
557 (ExtT == MVT::v4i32 && MemT == MVT::v4i16) ||
557 (ExtT == MVT::v4i32 && MemT == MVT::v4i16) ||
558 (ExtT == MVT::v2i64 && MemT == MVT::v2i32);
558 (ExtT == MVT::v2i64 && MemT == MVT::v2i32);
1269 if (ExtractedVecT == VecT)
lib/Target/X86/X86FastISel.cpp 300 if (VT == MVT::f64 && !X86ScalarSSEf64)
302 if (VT == MVT::f32 && !X86ScalarSSEf32)
305 if (VT == MVT::f80)
311 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
328 if (VT == MVT::i1)
779 if (TLI.getPointerTy(DL) == MVT::i64) {
1530 if (SrcVT == MVT::i1) {
1589 if (SrcVT == MVT::i1) {
1958 if (VT == MVT::i16) {
1962 } else if (VT == MVT::i32) {
1966 } else if (VT == MVT::i64) {
2155 !((Subtarget->hasSSE1() && RetVT == MVT::f32) ||
2156 (Subtarget->hasSSE2() && RetVT == MVT::f64)))
2208 (RetVT == MVT::f32) ? X86::VCMPSSZrr : X86::VCMPSDZrr;
2221 (RetVT == MVT::f32) ? X86::VMOVSSZrrk : X86::VMOVSDZrrk;
2239 (RetVT == MVT::f32) ? X86::VCMPSSrr : X86::VCMPSDrr;
2241 (RetVT == MVT::f32) ? X86::VBLENDVPSrr : X86::VBLENDVPDrr;
2437 bool Is64Bit = SrcVT == MVT::i64;
2695 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
2696 (FrameReg == X86::EBP && VT == MVT::i32)) &&
2958 if (VT == MVT::i8) {
3323 if (ArgVT == MVT::x86mmx)
3335 if (ArgVT == MVT::i1)
3349 if (ArgVT == MVT::i1) {
3666 SrcVT.getVectorElementType() == MVT::i1 ||
3667 DstVT.getVectorElementType() == MVT::i1)
3828 TLI.getPointerTy(DL) == MVT::i64) {
3836 TLI.getPointerTy(DL) == MVT::i32
3881 TLI.getPointerTy(DL) == MVT::i32
lib/Target/X86/X86ISelDAGToDAG.cpp 284 unsigned NegOpc = VT == MVT::i64 ? X86::NEG64r : X86::NEG32r;
904 if (VT.isVector() || VT == MVT::f128)
907 MVT VecVT = VT == MVT::f64 ? MVT::v2f64 : MVT::v4f32;
1624 Shift.getOperand(0).getSimpleValueType() == MVT::i32 &&
2533 if (VT == MVT::i32) {
3216 assert(V.getSimpleValueType() == MVT::i32 &&
3217 V.getOperand(0).getSimpleValueType() == MVT::i64 &&
3520 ROpc = NVT == MVT::i64 ? X86::BZHI64rr : X86::BZHI32rr;
3521 MOpc = NVT == MVT::i64 ? X86::BZHI64rm : X86::BZHI32rm;
3522 unsigned NewOpc = NVT == MVT::i64 ? X86::MOV32ri64 : X86::MOV32ri;
3531 ROpc = NVT == MVT::i64 ? X86::BEXTRI64ri : X86::BEXTRI32ri;
3532 MOpc = NVT == MVT::i64 ? X86::BEXTRI64mi : X86::BEXTRI32mi;
3536 ROpc = NVT == MVT::i64 ? X86::BEXTR64rr : X86::BEXTR32rr;
3537 MOpc = NVT == MVT::i64 ? X86::BEXTR64rm : X86::BEXTR32rm;
3538 unsigned NewOpc = NVT == MVT::i64 ? X86::MOV32ri64 : X86::MOV32ri;
3562 unsigned NewOpc = NVT == MVT::i64 ? X86::SHR64ri : X86::SHR32ri;
3743 Shift.getOperand(0).getSimpleValueType() == MVT::i32 &&
3775 if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal))
3788 if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal))
3906 if (!MaskLZ || (VT == MVT::i64 && MaskLZ == 32))
3910 if (VT == MVT::i64 && MaskLZ >= 32) {
3926 if (VT == MVT::i64 && MaskVal.getBitWidth() < 64) {
4113 assert(Setcc.getSimpleValueType().getVectorElementType() == MVT::i1 &&
4197 (CmpSVT == MVT::i32 || CmpSVT == MVT::i64)) {
4197 (CmpSVT == MVT::i32 || CmpSVT == MVT::i64)) {
4428 assert(Target.getSimpleValueType() == llvm::MVT::i32);
4446 NVT == MVT::f128) {
4479 if (NVT.isVector() && NVT.getVectorElementType() == MVT::i1) {
4672 if (NVT == MVT::i8)
4682 ReplaceUses(N1.getValue(1), SDValue(CNode, NVT == MVT::i8 ? 2 : 3));
4689 if (NVT == MVT::i8)
4698 ReplaceUses(SDValue(Node, 1), SDValue(CNode, NVT == MVT::i8 ? 1 : 2));
4847 if (NVT == MVT::i8) {
4988 unsigned TestOpc = CmpVT == MVT::i64 ? X86::TEST64rr
5015 if (CmpVT == MVT::i64 && !isInt<32>(Mask) &&
5051 (!(Mask & 0x80) || CmpVT == MVT::i8 ||
5059 (!(Mask & 0x8000) || CmpVT == MVT::i16 ||
5074 CmpVT == MVT::i32 ||
lib/Target/X86/X86ISelLowering.cpp 794 if (VT.getVectorElementType() == MVT::i1)
799 if (VT.getVectorElementType() == MVT::f16)
1926 if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
2134 if (VT == MVT::f32)
2136 else if (VT == MVT::f64)
2571 assert(VA.getValVT() == MVT::v64i1 &&
2739 assert(VA.getValVT() == MVT::v64i1 &&
2741 assert(NextVA.getValVT() == VA.getValVT() &&
2872 assert(VA.getValVT() == MVT::v64i1 &&
2888 if (VA.isExtInLoc() && (VA.getValVT().getScalarType() == MVT::i1)) {
2890 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
2890 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
2891 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
2891 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
3027 VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1 &&
3225 VA.getValVT() == MVT::v64i1 &&
3292 VA.getValVT().getScalarType() == MVT::i1 &&
3293 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
3293 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
3294 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
3294 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
3820 assert(VA.getValVT() == MVT::v64i1 &&
5370 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
5401 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
5417 } else if (EltVT == MVT::f32) {
5420 } else if (EltVT == MVT::f64) {
5436 VT.getVectorElementType() == MVT::i1) &&
5447 } else if (VT.getVectorElementType() == MVT::i1) {
6497 assert(VT.getScalarType() == MVT::i8 && "Byte vector expected");
6508 assert(VT.getScalarType() == MVT::i8 && "Byte vector expected");
6516 assert(VT.getScalarType() == MVT::i8 && "Byte vector expected");
6581 assert(VT.getScalarType() == MVT::i8 && "Byte vector expected");
7416 assert(((VT == MVT::v8i16 && Subtarget.hasSSE2()) ||
7417 ((VT == MVT::v16i8 || VT == MVT::v4i32) && Subtarget.hasSSE41())) &&
7417 ((VT == MVT::v16i8 || VT == MVT::v4i32) && Subtarget.hasSSE41())) &&
8192 if ((EltType == MVT::i64 && MaskVT == MVT::v8i1) || // for broadcastmb2q
8192 if ((EltType == MVT::i64 && MaskVT == MVT::v8i1) || // for broadcastmb2q
8193 (EltType == MVT::i32 && MaskVT == MVT::v16i1)) { // for broadcastmw2d
8193 (EltType == MVT::i32 && MaskVT == MVT::v16i1)) { // for broadcastmw2d
8398 assert(ShuffleVecVT.getVectorElementType() ==
8500 assert((VT.getVectorElementType() == MVT::i1) &&
8548 if (VT == MVT::v64i1 && !Subtarget.is64Bit()) {
8713 assert(VT.is256BitVector() && VT == V1.getSimpleValueType() &&
9078 if (((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget.hasSSE3()) ||
9078 if (((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget.hasSSE3()) ||
9079 ((VT == MVT::v8i16 || VT == MVT::v4i32) && Subtarget.hasSSSE3()) ||
9079 ((VT == MVT::v8i16 || VT == MVT::v4i32) && Subtarget.hasSSSE3()) ||
9080 ((VT == MVT::v8f32 || VT == MVT::v4f64) && Subtarget.hasAVX()) ||
9080 ((VT == MVT::v8f32 || VT == MVT::v4f64) && Subtarget.hasAVX()) ||
9081 ((VT == MVT::v16i16 || VT == MVT::v8i32) && Subtarget.hasAVX2())) {
9081 ((VT == MVT::v16i16 || VT == MVT::v8i32) && Subtarget.hasAVX2())) {
9107 if (VT == MVT::v8i32 || VT == MVT::v16i16) {
9107 if (VT == MVT::v8i32 || VT == MVT::v16i16) {
9147 if (VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
9147 if (VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
9147 if (VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
9148 VT == MVT::v16i16) {
9269 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
9269 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
9269 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
9591 if (VT.getVectorElementType() == MVT::i1 && Subtarget.hasAVX512())
9710 if (EltVT == MVT::i32 || EltVT == MVT::f32 || EltVT == MVT::f64 ||
9710 if (EltVT == MVT::i32 || EltVT == MVT::f32 || EltVT == MVT::f64 ||
9710 if (EltVT == MVT::i32 || EltVT == MVT::f32 || EltVT == MVT::f64 ||
9711 (EltVT == MVT::i64 && Subtarget.is64Bit())) {
9722 if (EltVT == MVT::i16 || EltVT == MVT::i8) {
9722 if (EltVT == MVT::i16 || EltVT == MVT::i8) {
10092 if (VT.getVectorElementType() == MVT::i1)
10659 if ((Subtarget.hasSSE41() || VT == MVT::v2i64 || VT == MVT::v2f64) &&
10659 if ((Subtarget.hasSSE41() || VT == MVT::v2i64 || VT == MVT::v2f64) &&
10811 if (SrcVT.getVectorElementType() == MVT::i16 && VT == MVT::v16i8 &&
10811 if (SrcVT.getVectorElementType() == MVT::i16 && VT == MVT::v16i8 &&
10839 if (Subtarget.hasSSE41() || PackSVT == MVT::i16) {
10904 if (EltVT == MVT::i64 && !Subtarget.is64Bit()) {
10910 if (EltVT == MVT::f32 || EltVT == MVT::f64) {
10910 if (EltVT == MVT::f32 || EltVT == MVT::f64) {
10915 MVT::getVectorVT(EltVT == MVT::f64 ? MVT::i64 : MVT::i32, Mask.size());
11564 assert(ByteVT == MVT::v16i8 &&
11595 assert((VT.getScalarType() == MVT::i32 || VT.getScalarType() == MVT::i64) &&
11595 assert((VT.getScalarType() == MVT::i32 || VT.getScalarType() == MVT::i64) &&
12289 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
12289 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
12300 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
12301 EltVT == MVT::i16) {
12311 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
12322 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
12322 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
12324 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
12493 if (!((Subtarget.hasSSE3() && VT == MVT::v2f64) ||
12502 unsigned Opcode = (VT == MVT::v2f64 && !Subtarget.hasAVX2())
12591 if (!Subtarget.is64Bit() && VT.getScalarType() == MVT::i64) {
12621 if (VT == MVT::v4f64 || VT == MVT::v4i64)
12621 if (VT == MVT::v4f64 || VT == MVT::v4i64)
12771 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
12772 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
12912 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
12913 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
12996 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
12997 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
13181 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
13182 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
13277 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
13278 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
13404 assert(VT.getVectorElementType() == MVT::i16 && "Bad input type!");
13964 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
13965 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
14172 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
14173 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
14517 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
14518 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
15516 assert((VT == MVT::v2f64 || VT == MVT::v4f64 || VT == MVT::v8f64) &&
15516 assert((VT == MVT::v2f64 || VT == MVT::v4f64 || VT == MVT::v8f64) &&
15516 assert((VT == MVT::v2f64 || VT == MVT::v4f64 || VT == MVT::v8f64) &&
15543 assert(VT == MVT::v32i8 && "Unexpected type!");
15579 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
15580 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
15687 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
15688 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
15785 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
15786 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
15884 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
15885 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
15995 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
15996 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
16095 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
16096 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
16358 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
16359 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
16412 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
16413 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
16465 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
16466 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
16528 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
16529 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
16597 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
16598 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
16650 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
16651 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
17051 bool Is1BitVector = (VT.getVectorElementType() == MVT::i1);
17294 if (VT == MVT::f32) {
17314 if (VT == MVT::i32 || VT == MVT::i64) {
17314 if (VT == MVT::i32 || VT == MVT::i64) {
17379 if (VecVT.getVectorElementType() == MVT::i1)
17551 if (EltVT == MVT::i1)
17589 if ((Subtarget.hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
17589 if ((Subtarget.hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
17590 (Subtarget.hasAVX2() && EltVT == MVT::i32)) {
17616 (EltVT == MVT::i32 || EltVT == MVT::f32 || EltVT == MVT::f64 ||
17616 (EltVT == MVT::i32 || EltVT == MVT::f32 || EltVT == MVT::f64 ||
17616 (EltVT == MVT::i32 || EltVT == MVT::f32 || EltVT == MVT::f64 ||
17617 EltVT == MVT::i64)) {
17624 if (VT == MVT::v8i16 || (VT == MVT::v16i8 && Subtarget.hasSSE41())) {
17624 if (VT == MVT::v8i16 || (VT == MVT::v16i8 && Subtarget.hasSSE41())) {
17626 if (VT == MVT::v8i16) {
17630 assert(VT == MVT::v16i8 && "PINSRB requires v16i8 vector");
17643 if (EltVT == MVT::f32) {
17673 if (EltVT == MVT::i32 || EltVT == MVT::i64)
17673 if (EltVT == MVT::i32 || EltVT == MVT::i64)
17707 if (OpVT == MVT::v4i32)
17720 assert(Op.getSimpleValueType().getVectorElementType() == MVT::i1);
17727 assert(Op.getSimpleValueType().getVectorElementType() == MVT::i1 &&
18306 assert((VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64) &&
18306 assert((VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64) &&
18306 assert((VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64) &&
18318 if (VT == MVT::i16)
18362 return ToVT == MVT::v4f32 || (Subtarget.hasAVX() && ToVT == MVT::v4f64);
18362 return ToVT == MVT::v4f32 || (Subtarget.hasAVX() && ToVT == MVT::v4f64);
18369 return ToVT == MVT::v4f32 || ToVT == MVT::v4f64;
18369 return ToVT == MVT::v4f32 || ToVT == MVT::v4f64;
18425 if (VT == MVT::f128)
18432 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
18432 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
18445 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(VT))
18447 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(VT) && Subtarget.is64Bit())
18454 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(VT) &&
18650 assert(N0.getSimpleValueType() == MVT::v2i32 && "Unexpected input type");
18705 bool Is128 = VecIntVT == MVT::v4i32;
18712 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
18712 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
18799 if (DstVT == MVT::f128)
18809 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget.is64Bit()))) {
18809 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget.is64Bit()))) {
18816 if (SrcVT == MVT::i32 && Subtarget.is64Bit()) {
18824 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
18824 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
18826 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
18828 if (Subtarget.is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
18828 if (Subtarget.is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
18833 if (SrcVT == MVT::i32) {
18843 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
19041 assert((VT.getVectorElementType() == MVT::i16 ||
19042 VT.getVectorElementType() == MVT::i32 ||
19043 VT.getVectorElementType() == MVT::i64) &&
19045 assert((InVT.getVectorElementType() == MVT::i8 ||
19046 InVT.getVectorElementType() == MVT::i16 ||
19047 InVT.getVectorElementType() == MVT::i32) &&
19053 if (InVT == MVT::v8i8) {
19098 assert((VT == MVT::v16i8 || VT == MVT::v16i16) && "Unexpected VT.");
19098 assert((VT == MVT::v16i8 || VT == MVT::v16i16) && "Unexpected VT.");
19115 assert(InVT.getVectorElementType() == MVT::i1 && "Unexpected input type!");
19172 if (SVT.getVectorElementType() == MVT::i1)
19297 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type.");
19331 if (InVT == MVT::v16i8) {
19378 if ((InVT == MVT::v8i64 || InVT == MVT::v16i32 || InVT == MVT::v16i64) &&
19378 if ((InVT == MVT::v8i64 || InVT == MVT::v16i32 || InVT == MVT::v16i64) &&
19378 if ((InVT == MVT::v8i64 || InVT == MVT::v16i32 || InVT == MVT::v16i64) &&
19399 if (VT.getVectorElementType() == MVT::i1)
19435 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
19435 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
19455 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
19455 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
19500 if (VT == MVT::v16i8 && InVT == MVT::v16i16) {
19500 if (VT == MVT::v16i8 && InVT == MVT::v16i16) {
19521 if (SrcVT == MVT::f128) {
19533 if (VT == MVT::v2i1 && SrcVT == MVT::v2f64) {
19533 if (VT == MVT::v2i1 && SrcVT == MVT::v2f64) {
19553 if (VT == MVT::v2i64 && SrcVT == MVT::v2f32) {
19553 if (VT == MVT::v2i64 && SrcVT == MVT::v2f32) {
19572 if (VT == MVT::i64)
19575 assert(VT == MVT::i32 && "Unexpected VT!");
19590 if (VT == MVT::i16 && UseSSEReg) {
19613 if (VT == MVT::f128) {
19618 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
19756 bool IsF128 = (VT == MVT::f128);
19757 assert((VT == MVT::f64 || VT == MVT::f32 || VT == MVT::f128 ||
19757 assert((VT == MVT::f64 || VT == MVT::f32 || VT == MVT::f128 ||
19757 assert((VT == MVT::f64 || VT == MVT::f32 || VT == MVT::f128 ||
19758 VT == MVT::v2f64 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
19758 VT == MVT::v2f64 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
19758 VT == MVT::v2f64 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
19759 VT == MVT::v8f32 || VT == MVT::v8f64 || VT == MVT::v16f32) &&
19759 VT == MVT::v8f32 || VT == MVT::v8f64 || VT == MVT::v16f32) &&
19759 VT == MVT::v8f32 || VT == MVT::v8f64 || VT == MVT::v16f32) &&
19773 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
19816 bool IsF128 = (VT == MVT::f128);
19817 assert((VT == MVT::f64 || VT == MVT::f32 || VT == MVT::f128 ||
19817 assert((VT == MVT::f64 || VT == MVT::f32 || VT == MVT::f128 ||
19817 assert((VT == MVT::f64 || VT == MVT::f32 || VT == MVT::f128 ||
19818 VT == MVT::v2f64 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
19818 VT == MVT::v2f64 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
19818 VT == MVT::v2f64 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
19819 VT == MVT::v8f32 || VT == MVT::v8f64 || VT == MVT::v16f32) &&
19819 VT == MVT::v8f32 || VT == MVT::v8f64 || VT == MVT::v16f32) &&
19819 VT == MVT::v8f32 || VT == MVT::v8f64 || VT == MVT::v16f32) &&
19832 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
19873 assert((OpVT == MVT::f32 || OpVT == MVT::f64) &&
19873 assert((OpVT == MVT::f32 || OpVT == MVT::f64) &&
19877 MVT VecVT = (OpVT == MVT::f32 ? MVT::v4f32 : MVT::v2f64);
20525 assert(VT.getVectorElementType() == MVT::i1 &&
20639 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
20639 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
20643 if (Subtarget.hasAVX512() && VT.getVectorElementType() == MVT::i1) {
20695 assert(VTOp0 == Op1.getSimpleValueType() &&
20702 assert((Subtarget.hasAVX512() || (VT == VTOp0)) &&
20706 if (VT.getVectorElementType() == MVT::i1) {
20859 if (VT == MVT::v2i64) {
20957 if (!(Subtarget.hasAVX512() && VT == MVT::v16i1) &&
20958 !(Subtarget.hasDQI() && VT == MVT::v8i1) &&
20959 !(Subtarget.hasBWI() && (VT == MVT::v32i1 || VT == MVT::v64i1)))
20959 !(Subtarget.hasBWI() && (VT == MVT::v32i1 || VT == MVT::v64i1)))
20973 if (Subtarget.hasDQI() && (VT == MVT::v8i1 || VT == MVT::v16i1))
20973 if (Subtarget.hasDQI() && (VT == MVT::v8i1 || VT == MVT::v16i1))
20975 if (Subtarget.hasBWI() && (VT == MVT::v32i1 || VT == MVT::v64i1))
20975 if (Subtarget.hasBWI() && (VT == MVT::v32i1 || VT == MVT::v64i1))
21063 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
21214 ((Subtarget.hasSSE2() && VT == MVT::f64) ||
21215 (Subtarget.hasSSE1() && VT == MVT::f32)) &&
21216 VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) {
21249 MVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
21254 MVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
21269 if ((VT == MVT::f64 || VT == MVT::f32) && Subtarget.hasAVX512()) {
21269 if ((VT == MVT::f64 || VT == MVT::f32) && Subtarget.hasAVX512()) {
21275 if (VT == MVT::v64i1 && !Subtarget.is64Bit()) {
21286 if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
21524 assert(InVT.getVectorElementType() == MVT::i1 && "Unexpected input type!");
21580 if (InVT.getVectorElementType() == MVT::i1)
21670 MVT DestVT = VT == MVT::v2i64 ? MVT::v4i32 : VT;
21692 if (VT == MVT::v2i64) {
21710 if (InVT.getVectorElementType() == MVT::i1)
21716 assert((VT.getVectorElementType() == MVT::i16 ||
21717 VT.getVectorElementType() == MVT::i32 ||
21718 VT.getVectorElementType() == MVT::i64) &&
21720 assert((InVT.getVectorElementType() == MVT::i8 ||
21721 InVT.getVectorElementType() == MVT::i16 ||
21722 InVT.getVectorElementType() == MVT::i32) &&
21726 if (InVT == MVT::v8i8) {
21919 if (RegVT.getVectorElementType() == MVT::i1) {
22520 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
22520 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
22542 if (SVT == MVT::i64)
22546 (ShAmt.getOperand(0).getSimpleValueType() == MVT::i16 ||
22547 ShAmt.getOperand(0).getSimpleValueType() == MVT::i8)) {
22549 MVT AmtTy = ShAmt.getSimpleValueType() == MVT::i8 ? MVT::v16i8 : MVT::v8i16;
22596 if (Mask.getSimpleValueType() == MVT::i64 && Subtarget.is32Bit()) {
22597 assert(MaskVT == MVT::v64i1 && "Expected v64i1 mask!");
24593 assert(EltVT == Src.getSimpleValueType().getVectorElementType() &&
24637 assert((EltVT == MVT::i8 || EltVT == MVT::i16) &&
24637 assert((EltVT == MVT::i8 || EltVT == MVT::i16) &&
24775 if (VT == MVT::i8) {
24797 if (VT == MVT::i8)
24884 if (VT == MVT::i16 || VT == MVT::i32)
24884 if (VT == MVT::i16 || VT == MVT::i32)
24887 if (VT.getScalarType() == MVT::i1)
24902 if (VT.getScalarType() == MVT::i1) {
24948 if (VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64) {
24948 if (VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64) {
24948 if (VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64) {
24961 if ((VT == MVT::v2i64 || VT == MVT::v4i64) && Subtarget.hasSSE41()) {
24961 if ((VT == MVT::v2i64 || VT == MVT::v4i64) && Subtarget.hasSSE41()) {
24993 if (VT == MVT::v8i16) {
25023 if (VT.getScalarType() == MVT::i1)
25035 if (VT == MVT::v16i8 || VT == MVT::v32i8 || VT == MVT::v64i8) {
25035 if (VT == MVT::v16i8 || VT == MVT::v32i8 || VT == MVT::v64i8) {
25035 if (VT == MVT::v16i8 || VT == MVT::v32i8 || VT == MVT::v64i8) {
25038 if ((VT == MVT::v16i8 && Subtarget.hasInt256()) ||
25039 (VT == MVT::v32i8 && Subtarget.canExtendTo512BW())) {
25087 if (VT == MVT::v4i32) {
25114 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
25114 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
25114 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
25176 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32) {
25176 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32) {
25176 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32) {
25177 assert((VT == MVT::v4i32 && Subtarget.hasSSE2()) ||
25178 (VT == MVT::v8i32 && Subtarget.hasInt256()) ||
25179 (VT == MVT::v16i32 && Subtarget.hasAVX512()));
25242 assert((VT == MVT::v16i8 || (VT == MVT::v32i8 && Subtarget.hasInt256()) ||
25242 assert((VT == MVT::v16i8 || (VT == MVT::v32i8 && Subtarget.hasInt256()) ||
25243 (VT == MVT::v64i8 && Subtarget.hasBWI())) &&
25253 if ((VT == MVT::v16i8 && Subtarget.hasInt256()) ||
25254 (VT == MVT::v32i8 && Subtarget.canExtendTo512BW())) {
25265 if (VT == MVT::v64i8 && IsSigned)
25269 if (VT == MVT::v32i8 && IsSigned) {
25312 if (IsSigned && VT == MVT::v16i8 && Subtarget.hasSSE41()) {
25354 } else if (IsSigned && VT == MVT::v16i8 && Subtarget.hasSSE41()) {
25495 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
25495 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
25512 if (VT == MVT::v2i64)
25514 if (VT == MVT::v4i64)
25524 if (VT == MVT::v2i64)
25526 if (VT == MVT::v4i64)
25548 if (((!Subtarget.hasXOP() && VT == MVT::v2i64) ||
25549 (Subtarget.hasInt256() && VT == MVT::v4i64)) &&
25553 if (VT == MVT::v16i8 || (Subtarget.hasInt256() && VT == MVT::v32i8) ||
25553 if (VT == MVT::v16i8 || (Subtarget.hasInt256() && VT == MVT::v32i8) ||
25554 VT == MVT::v64i8) {
25566 assert(VT == MVT::v64i8 && "Unexpected element type!");
25574 if (VT == MVT::v16i8 && Subtarget.hasXOP())
25633 if (((VT == MVT::v16i8 && !Subtarget.canExtendTo512DQ()) ||
25634 (VT == MVT::v32i8 && !Subtarget.canExtendTo512BW()) ||
25635 VT == MVT::v64i8) &&
25678 if (VT == MVT::v2i64 && Amt.getOpcode() == ISD::BITCAST &&
25702 if (!(VT == MVT::v8i16 || VT == MVT::v4i32 ||
25702 if (!(VT == MVT::v8i16 || VT == MVT::v4i32 ||
25703 (Subtarget.hasInt256() && VT == MVT::v16i16) ||
25704 (!Subtarget.hasAVX512() && VT == MVT::v16i8)))
25735 if (VT == MVT::v4i32) {
25744 if (VT == MVT::v8i16 && !Subtarget.hasAVX2()) {
25788 if (Subtarget.hasXOP() && (VT == MVT::v2i64 || VT == MVT::v4i32 ||
25788 if (Subtarget.hasXOP() && (VT == MVT::v2i64 || VT == MVT::v4i32 ||
25789 VT == MVT::v8i16 || VT == MVT::v16i8)) {
25789 VT == MVT::v8i16 || VT == MVT::v16i8)) {
25802 if (VT == MVT::v2i64 && Opc != ISD::SRA) {
25814 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget.hasInt256())) &&
25814 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget.hasInt256())) &&
25834 if (ConstantAmt && (VT == MVT::v8i16 || VT == MVT::v4i32 ||
25834 if (ConstantAmt && (VT == MVT::v8i16 || VT == MVT::v4i32 ||
25835 (VT == MVT::v16i16 && Subtarget.hasInt256()))) {
25862 (VT == MVT::v4i32 || Subtarget.hasSSE41() || Opc != ISD::SHL ||
25886 (VT == MVT::v8i16 || (VT == MVT::v16i16 && Subtarget.hasInt256()))) {
25886 (VT == MVT::v8i16 || (VT == MVT::v16i16 && Subtarget.hasInt256()))) {
25902 (VT == MVT::v8i16 || (VT == MVT::v16i16 && Subtarget.hasInt256())) &&
25902 (VT == MVT::v8i16 || (VT == MVT::v16i16 && Subtarget.hasInt256())) &&
25926 if (VT == MVT::v4i32) {
25981 if ((Subtarget.hasInt256() && VT == MVT::v8i16) ||
25982 (Subtarget.canExtendTo512DQ() && VT == MVT::v16i16) ||
25983 (Subtarget.canExtendTo512DQ() && VT == MVT::v16i8) ||
25984 (Subtarget.canExtendTo512BW() && VT == MVT::v32i8) ||
25985 (Subtarget.hasBWI() && Subtarget.hasVLX() && VT == MVT::v16i8)) {
25986 assert((!Subtarget.hasBWI() || VT == MVT::v32i8 || VT == MVT::v16i8) &&
25986 assert((!Subtarget.hasBWI() || VT == MVT::v32i8 || VT == MVT::v16i8) &&
26000 (VT == MVT::v16i8 || VT == MVT::v64i8 ||
26000 (VT == MVT::v16i8 || VT == MVT::v64i8 ||
26001 (VT == MVT::v32i8 && Subtarget.hasInt256())) &&
26015 if (VT == MVT::v16i8 && Subtarget.hasInt256()) {
26046 if (VT == MVT::v16i8 ||
26047 (VT == MVT::v32i8 && Subtarget.hasInt256() && !Subtarget.hasXOP()) ||
26048 (VT == MVT::v64i8 && Subtarget.hasBWI())) {
26154 if (Subtarget.hasInt256() && !Subtarget.hasXOP() && VT == MVT::v16i16) {
26172 if (VT == MVT::v8i16) {
26308 assert((VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8 ||
26308 assert((VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8 ||
26308 assert((VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8 ||
26309 ((VT == MVT::v8i32 || VT == MVT::v16i16 || VT == MVT::v32i8) &&
26309 ((VT == MVT::v8i32 || VT == MVT::v16i16 || VT == MVT::v32i8) &&
26309 ((VT == MVT::v8i32 || VT == MVT::v16i16 || VT == MVT::v32i8) &&
26413 assert(VT == MVT::v4i32 && "Only v4i32 vector rotate expected");
26732 if (InVT == MVT::v64i8) {
26743 if (InVT == MVT::v32i8 && !Subtarget.hasInt256()) {
26764 if (SrcVT == MVT::i64 && DstVT == MVT::v64i1) {
26764 if (SrcVT == MVT::i64 && DstVT == MVT::v64i1) {
26778 if ((SrcVT == MVT::v32i16 || SrcVT == MVT::v64i8) && DstVT.isVector() &&
26778 if ((SrcVT == MVT::v32i16 || SrcVT == MVT::v64i8) && DstVT.isVector() &&
26790 if ((SrcVT == MVT::v16i1 || SrcVT == MVT::v32i1) && DstVT.isScalarInteger()) {
26790 if ((SrcVT == MVT::v16i1 || SrcVT == MVT::v32i1) && DstVT.isScalarInteger()) {
26792 MVT SExtVT = SrcVT == MVT::v16i1 ? MVT::v16i8 : MVT::v32i8;
26799 assert((SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8 ||
26799 assert((SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8 ||
26799 assert((SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8 ||
26800 SrcVT == MVT::i64) && "Unexpected VT!");
26803 if (!(DstVT == MVT::f64 && SrcVT == MVT::i64) &&
26803 if (!(DstVT == MVT::f64 && SrcVT == MVT::i64) &&
26804 !(DstVT == MVT::x86mmx && SrcVT.isVector()))
26817 assert(SrcVT == MVT::i64 && !Subtarget.is64Bit() &&
26822 MVT V2X64VT = DstVT == MVT::f64 ? MVT::v2f64 : MVT::v2i64;
26825 if (DstVT == MVT::x86mmx)
26844 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
26853 if (EltVT == MVT::i64) {
26860 if (EltVT == MVT::i32) {
26889 assert(EltVT == MVT::i16 && "Unknown how to handle type");
26909 assert(EltVT == MVT::i8 && "Only vXi8 vector CTPOP lowering supported.");
26960 assert((VT.getVectorElementType() == MVT::i8 ||
26961 VT.getVectorElementType() == MVT::i16) && "Unexpected type");
27059 if (VT == MVT::v8i64 || VT == MVT::v16i32) {
27059 if (VT == MVT::v8i64 || VT == MVT::v16i32) {
27065 assert(VT.getScalarType() == MVT::i8 &&
27339 if (InVT == NVT)
27345 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
27401 if (VT == MVT::v2f32 || VT == MVT::v2i32) {
27401 if (VT == MVT::v2f32 || VT == MVT::v2i32) {
27422 if (IndexVT == MVT::v2i32)
27490 (ScalarVT == MVT::i8 || ScalarVT == MVT::i16))) &&
27490 (ScalarVT == MVT::i8 || ScalarVT == MVT::i16))) &&
27500 assert(Mask.getSimpleValueType().getScalarType() == MVT::i1 &&
27539 (ScalarVT == MVT::i8 || ScalarVT == MVT::i16))) &&
27539 (ScalarVT == MVT::i8 || ScalarVT == MVT::i16))) &&
27548 assert(Mask.getSimpleValueType().getScalarType() == MVT::i1 &&
27577 if (IndexVT == MVT::v2i32)
28012 if (InVT == MVT::v4i64 && VT == MVT::v4i8 && isTypeLegal(MVT::v8i64)) {
28019 if (Subtarget.hasVLX() && InVT == MVT::v8i64 && VT == MVT::v8i8 &&
29137 if (VT.getSimpleVT().getScalarType() == MVT::i1)
30438 unsigned XorRROpc = (PVT == MVT::i64) ? X86::XOR64rr : X86::XOR32rr;
30446 unsigned RdsspOpc = (PVT == MVT::i64) ? X86::RDSSPQ : X86::RDSSPD;
30450 unsigned PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
30495 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
30495 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
30539 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
30559 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
30688 unsigned XorRROpc = (PVT == MVT::i64) ? X86::XOR64rr : X86::XOR32rr;
30696 unsigned RdsspOpc = (PVT == MVT::i64) ? X86::RDSSPQ : X86::RDSSPD;
30701 unsigned TestRROpc = (PVT == MVT::i64) ? X86::TEST64rr : X86::TEST32rr;
30711 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
30729 unsigned SubRROpc = (PVT == MVT::i64) ? X86::SUB64rr : X86::SUB32rr;
30740 unsigned ShrRIOpc = (PVT == MVT::i64) ? X86::SHR64ri : X86::SHR32ri;
30741 unsigned Offset = (PVT == MVT::i64) ? 3 : 2;
30748 unsigned IncsspOpc = (PVT == MVT::i64) ? X86::INCSSPQ : X86::INCSSPD;
30763 unsigned ShlR1Opc = (PVT == MVT::i64) ? X86::SHL64r1 : X86::SHL32r1;
30770 unsigned MovRIOpc = (PVT == MVT::i64) ? X86::MOV64ri32 : X86::MOV32ri;
30789 unsigned DecROpc = (PVT == MVT::i64) ? X86::DEC64r : X86::DEC32r;
30813 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
30813 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
30817 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
30821 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
30829 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
30830 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
30893 assert((PVT == MVT::i64 || PVT == MVT::i32) && "Invalid Pointer Size!");
30893 assert((PVT == MVT::i64 || PVT == MVT::i32) && "Invalid Pointer Size!");
30902 Op = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
30905 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
30907 Op = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
32103 if (((MaskVT == MVT::v8i16 || MaskVT == MVT::v16i8) && Subtarget.hasSSE2()) ||
32103 if (((MaskVT == MVT::v8i16 || MaskVT == MVT::v16i8) && Subtarget.hasSSE2()) ||
32104 ((MaskVT == MVT::v16i16 || MaskVT == MVT::v32i8) && Subtarget.hasInt256()) ||
32104 ((MaskVT == MVT::v16i16 || MaskVT == MVT::v32i8) && Subtarget.hasInt256()) ||
32105 ((MaskVT == MVT::v32i16 || MaskVT == MVT::v64i8) && Subtarget.hasBWI())) {
32105 ((MaskVT == MVT::v32i16 || MaskVT == MVT::v64i8) && Subtarget.hasBWI())) {
32114 if ((MaskVT == MVT::v4f32 && Subtarget.hasSSE1()) ||
32154 (MaskVT == MVT::v16i16 && Subtarget.hasAVX2())) {
32160 if (MaskVT == MVT::v16i16) {
32560 (MaskVT == MVT::v8f32 || MaskVT == MVT::v8i32)) ||
32560 (MaskVT == MVT::v8f32 || MaskVT == MVT::v8i32)) ||
32562 (MaskVT == MVT::v8f64 || MaskVT == MVT::v8i64 ||
32562 (MaskVT == MVT::v8f64 || MaskVT == MVT::v8i64 ||
32563 MaskVT == MVT::v16f32 || MaskVT == MVT::v16i32)) ||
32563 MaskVT == MVT::v16f32 || MaskVT == MVT::v16i32)) ||
32564 (Subtarget.hasBWI() && MaskVT == MVT::v32i16) ||
32565 (Subtarget.hasBWI() && Subtarget.hasVLX() && MaskVT == MVT::v16i16) ||
32566 (Subtarget.hasVBMI() && MaskVT == MVT::v64i8) ||
32567 (Subtarget.hasVBMI() && Subtarget.hasVLX() && MaskVT == MVT::v32i8))) {
32578 (MaskVT == MVT::v8f64 || MaskVT == MVT::v8i64 ||
32578 (MaskVT == MVT::v8f64 || MaskVT == MVT::v8i64 ||
32579 MaskVT == MVT::v16f32 || MaskVT == MVT::v16i32)) ||
32579 MaskVT == MVT::v16f32 || MaskVT == MVT::v16i32)) ||
32581 (MaskVT == MVT::v4f64 || MaskVT == MVT::v4i64 ||
32581 (MaskVT == MVT::v4f64 || MaskVT == MVT::v4i64 ||
32582 MaskVT == MVT::v8f32 || MaskVT == MVT::v8i32)) ||
32582 MaskVT == MVT::v8f32 || MaskVT == MVT::v8i32)) ||
32583 (Subtarget.hasBWI() && MaskVT == MVT::v32i16) ||
32584 (Subtarget.hasBWI() && Subtarget.hasVLX() && MaskVT == MVT::v16i16) ||
32585 (Subtarget.hasVBMI() && MaskVT == MVT::v64i8) ||
32586 (Subtarget.hasVBMI() && Subtarget.hasVLX() && MaskVT == MVT::v32i8))) {
32609 (MaskVT == MVT::v8f64 || MaskVT == MVT::v8i64 ||
32609 (MaskVT == MVT::v8f64 || MaskVT == MVT::v8i64 ||
32610 MaskVT == MVT::v16f32 || MaskVT == MVT::v16i32)) ||
32610 MaskVT == MVT::v16f32 || MaskVT == MVT::v16i32)) ||
32612 (MaskVT == MVT::v4f64 || MaskVT == MVT::v4i64 ||
32612 (MaskVT == MVT::v4f64 || MaskVT == MVT::v4i64 ||
32613 MaskVT == MVT::v8f32 || MaskVT == MVT::v8i32)) ||
32613 MaskVT == MVT::v8f32 || MaskVT == MVT::v8i32)) ||
32614 (Subtarget.hasBWI() && MaskVT == MVT::v32i16) ||
32615 (Subtarget.hasBWI() && Subtarget.hasVLX() && MaskVT == MVT::v16i16) ||
32616 (Subtarget.hasVBMI() && MaskVT == MVT::v64i8) ||
32617 (Subtarget.hasVBMI() && Subtarget.hasVLX() && MaskVT == MVT::v32i8))) {
32658 ((MaskVT == MVT::v8f32 && Subtarget.hasAVX()) ||
32659 (MaskVT == MVT::v16f32 && Subtarget.hasAVX512()))) {
32675 (MaskVT == MVT::v2f64 || MaskVT == MVT::v4f64 || MaskVT == MVT::v4f32 ||
32675 (MaskVT == MVT::v2f64 || MaskVT == MVT::v4f64 || MaskVT == MVT::v4f32 ||
32675 (MaskVT == MVT::v2f64 || MaskVT == MVT::v4f64 || MaskVT == MVT::v4f32 ||
32676 MaskVT == MVT::v8f32)) {
32781 (MaskVT == MVT::v8f64 || MaskVT == MVT::v8i64 ||
32781 (MaskVT == MVT::v8f64 || MaskVT == MVT::v8i64 ||
32782 MaskVT == MVT::v16f32 || MaskVT == MVT::v16i32)) ||
32782 MaskVT == MVT::v16f32 || MaskVT == MVT::v16i32)) ||
32784 (MaskVT == MVT::v2f64 || MaskVT == MVT::v2i64 || MaskVT == MVT::v4f64 ||
32784 (MaskVT == MVT::v2f64 || MaskVT == MVT::v2i64 || MaskVT == MVT::v4f64 ||
32784 (MaskVT == MVT::v2f64 || MaskVT == MVT::v2i64 || MaskVT == MVT::v4f64 ||
32785 MaskVT == MVT::v4i64 || MaskVT == MVT::v4f32 || MaskVT == MVT::v4i32 ||
32785 MaskVT == MVT::v4i64 || MaskVT == MVT::v4f32 || MaskVT == MVT::v4i32 ||
32785 MaskVT == MVT::v4i64 || MaskVT == MVT::v4f32 || MaskVT == MVT::v4i32 ||
32786 MaskVT == MVT::v8f32 || MaskVT == MVT::v8i32)) ||
32786 MaskVT == MVT::v8f32 || MaskVT == MVT::v8i32)) ||
32787 (Subtarget.hasBWI() && MaskVT == MVT::v32i16) ||
32789 (MaskVT == MVT::v8i16 || MaskVT == MVT::v16i16)) ||
32789 (MaskVT == MVT::v8i16 || MaskVT == MVT::v16i16)) ||
32790 (Subtarget.hasVBMI() && MaskVT == MVT::v64i8) ||
32792 (MaskVT == MVT::v16i8 || MaskVT == MVT::v32i8)))) {
32792 (MaskVT == MVT::v16i8 || MaskVT == MVT::v32i8)))) {
33612 assert(VT == MVT::v4f32 && "INSERTPS ValueType must be MVT::v4f32");
33732 assert(VT.getVectorElementType() == MVT::i16 && "Bad word shuffle type!");
35298 if (SExtVT == MVT::v16i8 || SExtVT == MVT::v32i8 || SExtVT == MVT::v64i8) {
35298 if (SExtVT == MVT::v16i8 || SExtVT == MVT::v32i8 || SExtVT == MVT::v64i8) {
35298 if (SExtVT == MVT::v16i8 || SExtVT == MVT::v32i8 || SExtVT == MVT::v64i8) {
35301 if (SExtVT == MVT::v8i16)
42907 assert(VT == MVT::i32 && "Unexpected result type");
44307 if (Op0.getOpcode() == X86ISD::MOVDDUP && VT == MVT::v4f64 &&
44347 if (!IsSplat && NumOps == 2 && (VT == MVT::v8f32 || VT == MVT::v8i32) &&
44347 if (!IsSplat && NumOps == 2 && (VT == MVT::v8f32 || VT == MVT::v8i32) &&
44408 bool IsI1Vector = OpVT.getVectorElementType() == MVT::i1;
44461 SubVec.getOperand(0).getSimpleValueType() == OpVT &&
44632 if (VT.getScalarType() == MVT::i1)
44706 if (VT == MVT::v2f64 && InVecVT == MVT::v4f64) {
45810 if (VT == MVT::i1)
45812 if (VT == MVT::i8)
45814 if (VT == MVT::i16)
45818 if (VT == MVT::i32)
45820 if (VT == MVT::i64)
45826 if (VT == MVT::i32 || VT == MVT::f32)
45826 if (VT == MVT::i32 || VT == MVT::f32)
45828 if (VT == MVT::i16)
45830 if (VT == MVT::i8 || VT == MVT::i1)
45830 if (VT == MVT::i8 || VT == MVT::i1)
45832 if (VT == MVT::i64 || VT == MVT::f64)
45832 if (VT == MVT::i64 || VT == MVT::f64)
45839 if (VT == MVT::i32 || VT == MVT::f32)
45839 if (VT == MVT::i32 || VT == MVT::f32)
45841 if (VT == MVT::i16)
45843 if (VT == MVT::i8 || VT == MVT::i1)
45843 if (VT == MVT::i8 || VT == MVT::i1)
45845 if (VT == MVT::i64)
45850 if (VT == MVT::i8 || VT == MVT::i1)
45850 if (VT == MVT::i8 || VT == MVT::i1)
45852 if (VT == MVT::i16)
45854 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget.is64Bit())
45854 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget.is64Bit())
45858 if (VT == MVT::i8 || VT == MVT::i1)
45858 if (VT == MVT::i8 || VT == MVT::i1)
45860 if (VT == MVT::i16)
45862 if (VT == MVT::i32 || !Subtarget.is64Bit())
45868 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
45870 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
45950 if (VT == MVT::i1)
45952 if (VT == MVT::i8)
45954 if (VT == MVT::i16)
45958 if (VT == MVT::i32)
45960 if (VT == MVT::i64)
46029 if (TRI->isTypeLegalForClass(*Res.second, VT) || VT == MVT::Other)
46087 if (VT == MVT::f32 || VT == MVT::i32)
46087 if (VT == MVT::f32 || VT == MVT::i32)
46089 else if (VT == MVT::f64 || VT == MVT::i64)
46089 else if (VT == MVT::f64 || VT == MVT::i64)
46103 if (VT == MVT::i1)
46105 else if (VT == MVT::i8)
46107 else if (VT == MVT::i16)
46109 else if (VT == MVT::i32)
46111 else if (VT == MVT::i64)
lib/Target/X86/X86InterleavedAccess.cpp 416 if (VT == MVT::v16i8) {
lib/Target/X86/X86TargetTransformInfo.cpp 221 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) {
435 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX())
437 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX())
439 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41())
441 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41())
572 if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
649 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2())
662 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) ||
662 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) ||
663 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX()))
663 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX()))
924 LT.second.getVectorElementType() ==
usr/include/c++/7.4.0/bits/predefined_ops.h 241 { return *__it == _M_value; }
usr/include/c++/7.4.0/bits/stl_algobase.h 800 if (!(*__first1 == *__first2))
usr/include/c++/7.4.0/bits/stl_pair.h 449 { return __x.first == __y.first && __x.second == __y.second; }
utils/TableGen/CodeGenDAGPatterns.cpp 37 return VT.isInteger() || VT == MVT::iPTR;
1425 if (P.second == MVT::isVoid)
utils/TableGen/CodeGenTarget.cpp 821 return ParamType == MVT::iPTR || ParamType == MVT::iPTRAny;
821 return ParamType == MVT::iPTR || ParamType == MVT::iPTRAny;
utils/TableGen/GlobalISelEmitter.cpp 1593 if (VTy.getMachineValueType() == MVT::iPTR && OperandIsAPointer) {
utils/TableGen/InfoByHwMode.cpp 52 return getSimple() == T.getSimple();
utils/unittest/googletest/include/gtest/gtest.h 1392 if (lhs == rhs) {