reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/X86/X86GenSubtargetInfo.inc

22918   unsigned ProcessorID = getSchedModel().getProcessorID();
23009   unsigned ProcessorID = getSchedModel().getProcessorID();
23051   unsigned ProcessorID = getSchedModel().getProcessorID();

include/llvm/CodeGen/BasicTTIImpl.h

  468     else if (ST->getSchedModel().LoopMicroOpBufferSize > 0)
  469       MaxOps = ST->getSchedModel().LoopMicroOpBufferSize;
  513       return getST()->getSchedModel().DefaultLoadLatency;

include/llvm/CodeGen/MachinePipeliner.h

  443       : STI(ST), SM(ST->getSchedModel()), UseDFA(ST->useDFAforSMS()),

lib/CodeGen/EarlyIfConversion.cpp

  911   SchedModel = STI.getSchedModel();

lib/CodeGen/MachineCombiner.cpp

  636   SchedModel = STI->getSchedModel();

lib/CodeGen/MachinePipeliner.cpp

  932     if (STI && STI->getSchedModel().hasInstrSchedModel()) {
  934           STI->getSchedModel().getSchedClassDesc(SchedClass);
  946             STI->getSchedModel().getProcResource(PRE.ProcResourceIdx);
  975     if (STI && STI->getSchedModel().hasInstrSchedModel()) {
  977           STI->getSchedModel().getSchedClassDesc(SchedClass);

lib/CodeGen/TargetSchedule.cpp

   65   SchedModel = TSInfo->getSchedModel();

lib/CodeGen/TargetSubtargetInfo.cpp

   54   return getSchedModel().PostRAScheduler;

lib/MC/MCDisassembler/Disassembler.cpp

  197   const MCSchedModel SCModel = STI->getSchedModel();

lib/MC/MCSchedule.cpp

   91   const MCSchedModel &SM = STI.getSchedModel();

lib/MC/MCSubtargetInfo.cpp

  315   InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles,

lib/MCA/Context.cpp

   32   const MCSchedModel &SM = STI.getSchedModel();

lib/MCA/HardwareUnits/RegisterFile.cpp

  417   const MCSchedModel &SM = STI.getSchedModel();

lib/MCA/InstrBuilder.cpp

   33   const MCSchedModel &SM = STI.getSchedModel();
   35   computeProcResourceMasks(STI.getSchedModel(), ProcResourceMasks);
   42   const MCSchedModel &SM = STI.getSchedModel();
  250   const MCSchedModel &SM = STI.getSchedModel();
  510   assert(STI.getSchedModel().hasInstrSchedModel() &&
  516   const MCSchedModel &SM = STI.getSchedModel();
  623     unsigned ProcID = STI.getSchedModel().getProcessorID();

lib/MCA/Stages/DispatchStage.cpp

   35     DispatchWidth = Subtarget.getSchedModel().IssueWidth;

lib/Target/AArch64/AArch64ConditionalCompares.cpp

  936   SchedModel = MF.getSubtarget().getSchedModel();

lib/Target/ARM/ARMISelLowering.cpp

 1448   PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();

lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp

  401   const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
  412   const InstrItinerary *II = STI.getSchedModel().InstrItineraries;

lib/Target/X86/X86ISelLowering.cpp

 1899   PredictableSelectIsExpensive = Subtarget.getSchedModel().isOutOfOrder();

tools/llvm-exegesis/lib/Analysis.cpp

  142       SubtargetInfo_->getSchedModel().getSchedClassDesc(SchedClassId);
  380     const auto &SM = SubtargetInfo_->getSchedModel();
  416       writeEscaped<kEscapeHtml>(OS, SubtargetInfo_->getSchedModel()

tools/llvm-exegesis/lib/SchedClassResolution.cpp

   53   const auto &SM = STI.getSchedModel();
  210       SCDesc(STI.getSchedModel().getSchedClassDesc(ResolvedSchedClassId)),
  214           STI.getSchedModel(), NonRedundantWriteProcRes)) {
  222   const auto &SM = STI.getSchedModel();
  234   const bool WasVariant = SchedClassId && SubtargetInfo.getSchedModel()
  249   const auto &SchedModel = STI.getSchedModel();

tools/llvm-mca/Views/BottleneckAnalysis.cpp

  454     : STI(sti), MCIP(Printer), Tracker(STI.getSchedModel()), DG(S.size() * 3),
  620     const MCSchedModel &SM = STI.getSchedModel();

tools/llvm-mca/Views/InstructionInfoView.cpp

   23   const MCSchedModel &SM = STI.getSchedModel();

tools/llvm-mca/Views/RegisterFileStatistics.cpp

   22   const MCSchedModel &SM = STI.getSchedModel();
  118     assert(STI.getSchedModel().hasExtraProcessorInfo() &&
  121         STI.getSchedModel().getExtraProcessorInfo();

tools/llvm-mca/Views/ResourcePressureView.cpp

   27   const MCSchedModel &SM = STI.getSchedModel();
  108   const MCSchedModel &SM = STI.getSchedModel();
  151   printColumnNames(FOS, STI.getSchedModel());

tools/llvm-mca/Views/SchedulerStatistics.cpp

   22     : SM(STI.getSchedModel()), LQResourceID(0), SQResourceID(0), NumIssued(0),
   25       Usage(STI.getSchedModel().NumProcResourceKinds, {0, 0, 0}) {

tools/llvm-mca/Views/TimelineView.cpp

   46   const MCSchedModel &SM = STI.getSchedModel();
  167                    CumulativeExecutions, STI.getSchedModel().MicroOpBufferSize);

tools/llvm-mca/llvm-mca.cpp

  334   if (!PrintInstructionTables && !STI->getSchedModel().isOutOfOrder()) {
  340   if (!STI->getSchedModel().hasInstrSchedModel()) {
  346     if (STI->getSchedModel().InstrItineraries)
  427   const MCSchedModel &SM = STI->getSchedModel();

unittests/tools/llvm-exegesis/PowerPC/AnalysisTest.cpp

   39     const auto &SM = STI->getSchedModel();
   74       computeIdealizedProcResPressure(STI->getSchedModel(), {{ALUIdx, 2}});
   80       computeIdealizedProcResPressure(STI->getSchedModel(), {{ALUEIdx, 2}});
   86       computeIdealizedProcResPressure(STI->getSchedModel(), {{ALUIdx, 1}, {IPAGENIdx, 1}});

unittests/tools/llvm-exegesis/X86/SchedClassResolutionTest.cpp

   31     const auto &SM = STI.getSchedModel();
   68       computeIdealizedProcResPressure(STI.getSchedModel(), {{P0Idx, 2}});
   74       computeIdealizedProcResPressure(STI.getSchedModel(), {{P05Idx, 2}});
   81       STI.getSchedModel(), {{P05Idx, 2}, {P0156Idx, 2}});
   90       STI.getSchedModel(), {{P1Idx, 1}, {P05Idx, 1}, {P0156Idx, 2}});