|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/TargetRegisterInfo.h 119 return RC != this && hasSubClassEq(RC);
136 return RC->hasSubClassEq(this);
lib/CodeGen/GlobalISel/RegisterBank.cpp 47 if (!RC.hasSubClassEq(&SubRC))
lib/CodeGen/MachineFunction.cpp 596 RC->hasSubClassEq(VRegRC))) &&
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 574 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
lib/CodeGen/TargetInstrInfo.cpp 457 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
lib/Target/AArch64/AArch64ISelLowering.cpp 6054 !AArch64::GPR32allRegClass.hasSubClassEq(Res.second) &&
6055 !AArch64::GPR64allRegClass.hasSubClassEq(Res.second))
lib/Target/AArch64/AArch64InstrInfo.cpp 436 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg));
513 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) ||
514 AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
527 if (AArch64::FPR64RegClass.hasSubClassEq(RC) ||
528 AArch64::FPR32RegClass.hasSubClassEq(RC)) {
1077 } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&
2820 if (AArch64::FPR8RegClass.hasSubClassEq(RC))
2824 if (AArch64::FPR16RegClass.hasSubClassEq(RC))
2828 if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
2834 } else if (AArch64::FPR32RegClass.hasSubClassEq(RC))
2838 if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {
2844 } else if (AArch64::FPR64RegClass.hasSubClassEq(RC)) {
2846 } else if (AArch64::WSeqPairsClassRegClass.hasSubClassEq(RC)) {
2854 if (AArch64::FPR128RegClass.hasSubClassEq(RC))
2856 else if (AArch64::DDRegClass.hasSubClassEq(RC)) {
2860 } else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {
2868 if (AArch64::DDDRegClass.hasSubClassEq(RC)) {
2875 if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {
2879 } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {
2886 if (AArch64::QQQRegClass.hasSubClassEq(RC)) {
2893 if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {
2951 if (AArch64::FPR8RegClass.hasSubClassEq(RC))
2955 if (AArch64::FPR16RegClass.hasSubClassEq(RC))
2959 if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
2965 } else if (AArch64::FPR32RegClass.hasSubClassEq(RC))
2969 if (AArch64::GPR64allRegClass.hasSubClassEq(RC)) {
2975 } else if (AArch64::FPR64RegClass.hasSubClassEq(RC)) {
2977 } else if (AArch64::WSeqPairsClassRegClass.hasSubClassEq(RC)) {
2985 if (AArch64::FPR128RegClass.hasSubClassEq(RC))
2987 else if (AArch64::DDRegClass.hasSubClassEq(RC)) {
2991 } else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {
2999 if (AArch64::DDDRegClass.hasSubClassEq(RC)) {
3006 if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {
3010 } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {
3017 if (AArch64::QQQRegClass.hasSubClassEq(RC)) {
3024 if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {
lib/Target/AMDGPU/SIInstrInfo.cpp 6266 return RI.getRegClass(RCID)->hasSubClassEq(&AMDGPU::SGPR_128RegClass);
lib/Target/ARC/ARCInstrInfo.cpp 311 assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&
338 assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&
lib/Target/ARM/ARMAsmPrinter.cpp 374 ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) {
lib/Target/ARM/ARMBaseInstrInfo.cpp 1042 if (ARM::HPRRegClass.hasSubClassEq(RC)) {
1053 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1060 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1067 } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) {
1078 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1085 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1106 if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) {
1122 } else if (ARM::QPRRegClass.hasSubClassEq(RC) &&
1134 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1158 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1158 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1184 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1284 if (ARM::HPRRegClass.hasSubClassEq(RC)) {
1294 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1300 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1306 } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) {
1316 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1322 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1348 if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) {
1361 } else if (ARM::QPRRegClass.hasSubClassEq(RC) &&
1372 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1395 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1395 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1419 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
lib/Target/ARM/Thumb2InstrInfo.cpp 148 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
158 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
190 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
199 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
lib/Target/ARM/ThumbRegisterInfo.cpp 48 if (ARM::tGPRRegClass.hasSubClassEq(RC))
lib/Target/AVR/AVRRegisterInfo.cpp 283 if(this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) {
lib/Target/Hexagon/HexagonBitSimplify.cpp 1877 return OpRC->hasSubClassEq(RRC);
lib/Target/Hexagon/HexagonConstPropagation.cpp 2353 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC))
2355 if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC))
2357 if (Hexagon::PredRegsRegClass.hasSubClassEq(RC))
lib/Target/Hexagon/HexagonFrameLowering.cpp 2044 if (HaveRC->hasSubClassEq(NewRC))
2046 if (NewRC->hasSubClassEq(HaveRC))
lib/Target/Hexagon/HexagonInstrInfo.cpp 900 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
904 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
908 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
912 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
916 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
920 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
932 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
965 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
968 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
971 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
974 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
977 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
980 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
991 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
lib/Target/Lanai/LanaiInstrInfo.cpp 59 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) {
79 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) {
lib/Target/Mips/Mips16InstrInfo.cpp 120 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
139 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
lib/Target/Mips/MipsSEInstrInfo.cpp 259 if (Mips::GPR32RegClass.hasSubClassEq(RC))
261 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
263 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
265 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
267 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
269 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
271 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
273 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
275 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
288 else if (Mips::LO32RegClass.hasSubClassEq(RC))
290 else if (Mips::LO64RegClass.hasSubClassEq(RC))
292 else if (Mips::HI32RegClass.hasSubClassEq(RC))
294 else if (Mips::HI64RegClass.hasSubClassEq(RC))
296 else if (Mips::DSPRRegClass.hasSubClassEq(RC))
303 if (Mips::HI32RegClass.hasSubClassEq(RC)) {
306 } else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
309 } else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
312 } else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
337 if (Mips::GPR32RegClass.hasSubClassEq(RC))
339 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
341 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
343 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
345 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
347 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
349 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
351 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
353 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
366 else if (Mips::HI32RegClass.hasSubClassEq(RC))
368 else if (Mips::HI64RegClass.hasSubClassEq(RC))
370 else if (Mips::LO32RegClass.hasSubClassEq(RC))
372 else if (Mips::LO64RegClass.hasSubClassEq(RC))
374 else if (Mips::DSPRRegClass.hasSubClassEq(RC))
lib/Target/PowerPC/PPCInstrInfo.cpp 775 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
776 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
777 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
778 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
806 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
807 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
809 PPC::GPRCRegClass.hasSubClassEq(RC) ||
810 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
1034 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1035 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1037 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1038 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1040 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1042 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1044 } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1046 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1048 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1050 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1052 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1054 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1056 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1058 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1060 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1062 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1064 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1066 } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1120 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1121 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1123 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1124 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1126 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1128 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1130 } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1132 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1134 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1136 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1138 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1140 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1142 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1144 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1146 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1148 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1150 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1152 } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1213 if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1214 PPC::CRBITRCRegClass.hasSubClassEq(RC))
1217 if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1265 if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1266 PPC::CRBITRCRegClass.hasSubClassEq(RC))
1269 if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
lib/Target/PowerPC/PPCVSXCopy.cpp 54 return RC->hasSubClassEq(MRI.getRegClass(Reg));
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 162 return RC->hasSubClassEq(MRI->getRegClass(Reg));
lib/Target/RISCV/RISCVInstrInfo.cpp 121 if (RISCV::GPRRegClass.hasSubClassEq(RC))
124 else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
126 else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
148 if (RISCV::GPRRegClass.hasSubClassEq(RC))
151 else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
153 else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
lib/Target/Sparc/SparcInstrInfo.cpp 421 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
424 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
459 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
462 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
lib/Target/SystemZ/SystemZInstrInfo.cpp 553 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) ||
554 SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
555 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
580 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {
595 } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
lib/Target/SystemZ/SystemZRegisterInfo.cpp 34 if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
38 if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) ||
lib/Target/X86/X86DomainReassignment.cpp 45 return X86::GR64RegClass.hasSubClassEq(RC) ||
46 X86::GR32RegClass.hasSubClassEq(RC) ||
47 X86::GR16RegClass.hasSubClassEq(RC) ||
48 X86::GR8RegClass.hasSubClassEq(RC);
53 return X86::VK16RegClass.hasSubClassEq(RC);
69 if (X86::GR8RegClass.hasSubClassEq(SrcRC))
71 if (X86::GR16RegClass.hasSubClassEq(SrcRC))
73 if (X86::GR32RegClass.hasSubClassEq(SrcRC))
75 if (X86::GR64RegClass.hasSubClassEq(SrcRC))
lib/Target/X86/X86InstrInfo.cpp 2850 if (X86::GR16RegClass.hasSubClassEq(RC) ||
2851 X86::GR32RegClass.hasSubClassEq(RC) ||
2852 X86::GR64RegClass.hasSubClassEq(RC)) {
3073 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3077 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3081 if (X86::VK16RegClass.hasSubClassEq(RC))
3083 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3086 if (X86::GR32RegClass.hasSubClassEq(RC))
3088 if (X86::FR32XRegClass.hasSubClassEq(RC))
3096 if (X86::RFP32RegClass.hasSubClassEq(RC))
3098 if (X86::VK32RegClass.hasSubClassEq(RC)) {
3104 if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
3105 X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
3106 X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
3107 X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
3108 X86::VK16PAIRRegClass.hasSubClassEq(RC))
3112 if (X86::GR64RegClass.hasSubClassEq(RC))
3114 if (X86::FR64XRegClass.hasSubClassEq(RC))
3122 if (X86::VR64RegClass.hasSubClassEq(RC))
3124 if (X86::RFP64RegClass.hasSubClassEq(RC))
3126 if (X86::VK64RegClass.hasSubClassEq(RC)) {
3132 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3135 if (X86::VR128XRegClass.hasSubClassEq(RC)) {
3158 if (X86::BNDRRegClass.hasSubClassEq(RC)) {
3167 assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
3186 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
lib/Target/X86/X86InstructionSelector.cpp 296 if (!OldRC || !DstRC->hasSubClassEq(OldRC)) {
lib/Target/X86/X86RegisterBankInfo.cpp 46 if (X86::GR8RegClass.hasSubClassEq(&RC) ||
47 X86::GR16RegClass.hasSubClassEq(&RC) ||
48 X86::GR32RegClass.hasSubClassEq(&RC) ||
49 X86::GR64RegClass.hasSubClassEq(&RC) ||
50 X86::LOW32_ADDR_ACCESSRegClass.hasSubClassEq(&RC) ||
51 X86::LOW32_ADDR_ACCESS_RBPRegClass.hasSubClassEq(&RC))
54 if (X86::FR32XRegClass.hasSubClassEq(&RC) ||
55 X86::FR64XRegClass.hasSubClassEq(&RC) ||
56 X86::VR128XRegClass.hasSubClassEq(&RC) ||
57 X86::VR256XRegClass.hasSubClassEq(&RC) ||
58 X86::VR512RegClass.hasSubClassEq(&RC))