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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc20060 unsigned TV = Table[RC->getID()][Idx];
20177 return RCWeightTable[RC->getID()];
20324 return &RCSetsTable[RCSetStartTable[RC->getID()]];
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc47918 unsigned TV = Table[RC->getID()][Idx];
48041 return RCWeightTable[RC->getID()];
48685 return &RCSetsTable[RCSetStartTable[RC->getID()]];
gen/lib/Target/AMDGPU/R600GenRegisterInfo.inc12180 unsigned TV = Table[RC->getID()][Idx];
12226 return RCWeightTable[RC->getID()];
12329 return &RCSetsTable[RCSetStartTable[RC->getID()]];
gen/lib/Target/ARC/ARCGenRegisterInfo.inc 709 return RCWeightTable[RC->getID()];
761 return &RCSetsTable[RCSetStartTable[RC->getID()]];
gen/lib/Target/ARM/ARMGenRegisterInfo.inc15648 unsigned TV = Table[RC->getID()][Idx];
15779 return RCWeightTable[RC->getID()];
15919 return &RCSetsTable[RCSetStartTable[RC->getID()]];
gen/lib/Target/AVR/AVRGenRegisterInfo.inc 1564 unsigned TV = Table[RC->getID()][Idx];
1591 return RCWeightTable[RC->getID()];
1661 return &RCSetsTable[RCSetStartTable[RC->getID()]];
gen/lib/Target/BPF/BPFGenRegisterInfo.inc 589 unsigned TV = Table[RC->getID()][Idx];
600 return RCWeightTable[RC->getID()];
647 return &RCSetsTable[RCSetStartTable[RC->getID()]];
gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc 3525 unsigned TV = Table[RC->getID()][Idx];
3559 return RCWeightTable[RC->getID()];
3624 return &RCSetsTable[RCSetStartTable[RC->getID()]];
gen/lib/Target/Lanai/LanaiGenRegisterInfo.inc 812 unsigned TV = Table[RC->getID()][Idx];
824 return RCWeightTable[RC->getID()];
873 return &RCSetsTable[RCSetStartTable[RC->getID()]];
gen/lib/Target/MSP430/MSP430GenRegisterInfo.inc 522 unsigned TV = Table[RC->getID()][Idx];
533 return RCWeightTable[RC->getID()];
580 return &RCSetsTable[RCSetStartTable[RC->getID()]];
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 7141 unsigned TV = Table[RC->getID()][Idx];
7220 return RCWeightTable[RC->getID()];
7316 return &RCSetsTable[RCSetStartTable[RC->getID()]];
gen/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc 1198 return RCWeightTable[RC->getID()];
1281 return &RCSetsTable[RCSetStartTable[RC->getID()]];
gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc 5501 unsigned TV = Table[RC->getID()][Idx];
5544 return RCWeightTable[RC->getID()];
5630 return &RCSetsTable[RCSetStartTable[RC->getID()]];
gen/lib/Target/RISCV/RISCVGenRegisterInfo.inc 1693 unsigned TV = Table[RC->getID()][Idx];
1714 return RCWeightTable[RC->getID()];
1776 return &RCSetsTable[RCSetStartTable[RC->getID()]];
gen/lib/Target/Sparc/SparcGenRegisterInfo.inc 2660 unsigned TV = Table[RC->getID()][Idx];
2682 return RCWeightTable[RC->getID()];
2741 return &RCSetsTable[RCSetStartTable[RC->getID()]];
gen/lib/Target/SystemZ/SystemZGenRegisterInfo.inc 2819 unsigned TV = Table[RC->getID()][Idx];
2850 return RCWeightTable[RC->getID()];
2907 return &RCSetsTable[RCSetStartTable[RC->getID()]];
gen/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc 472 return RCWeightTable[RC->getID()];
534 return &RCSetsTable[RCSetStartTable[RC->getID()]];
gen/lib/Target/X86/X86GenRegisterInfo.inc 9594 unsigned TV = Table[RC->getID()][Idx];
9721 return RCWeightTable[RC->getID()];
9866 return &RCSetsTable[RCSetStartTable[RC->getID()]];
gen/lib/Target/XCore/XCoreGenRegisterInfo.inc 472 return RCWeightTable[RC->getID()];
519 return &RCSetsTable[RCSetStartTable[RC->getID()]];
include/llvm/CodeGen/RegisterClassInfo.h 74 const RCInfo &RCI = RegClass[RC->getID()];
include/llvm/CodeGen/TargetRegisterInfo.h 124 unsigned ID = RC->getID();
654 return RCInfos[getNumRegClasses() * HwMode + RC.getID()];
lib/CodeGen/GlobalISel/RegisterBank.cpp 62 return ContainedRegClasses.test(RC.getID());
lib/CodeGen/RegisterClassInfo.cpp 92 RCInfo &RCI = RegClass[RC->getID()];
lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp 60 RegLimit[RC->getID()] = TRI->getRegPressureLimit(RC, *IS->MF);
95 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
133 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
330 && TLI->getRegClassFor(VT)->getID() == RCId)
341 && TLI->getRegClassFor(VT)->getID() == RCId)
361 RegBalance += rawRegPressureDelta(SU, RC->getID());
365 if ((RegPressure[RC->getID()] +
366 rawRegPressureDelta(SU, RC->getID()) > 0) &&
367 (RegPressure[RC->getID()] +
368 rawRegPressureDelta(SU, RC->getID()) >= RegLimit[RC->getID()]))
368 rawRegPressureDelta(SU, RC->getID()) >= RegLimit[RC->getID()]))
369 RegBalance += rawRegPressureDelta(SU, RC->getID());
480 RegPressure[RC->getID()] += numberRCValSuccInSU(SU, RC->getID());
480 RegPressure[RC->getID()] += numberRCValSuccInSU(SU, RC->getID());
491 if (RegPressure[RC->getID()] >
492 (numberRCValPredInSU(SU, RC->getID())))
493 RegPressure[RC->getID()] -= numberRCValPredInSU(SU, RC->getID());
493 RegPressure[RC->getID()] -= numberRCValPredInSU(SU, RC->getID());
494 else RegPressure[RC->getID()] = 0;
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 326 RegClass = RC->getID();
335 RegClass = RC->getID();
343 RegClass = RC->getID();
348 RegClass = TLI->getRepRegClassFor(VT)->getID();
1768 RegLimit[RC->getID()] = tri->getRegPressureLimit(RC, MF);
2074 unsigned Id = RC->getID();
2119 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2150 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2165 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2273 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2285 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2294 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
2313 unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 959 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 282 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i64);
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 227 switch (RC.getID()) {
lib/Target/AArch64/AArch64RegisterInfo.cpp 542 switch (RC->getID()) {
lib/Target/AMDGPU/SIFixupVectorISel.cpp 128 if (AMDGPU::getRegBitWidth(IdxRC->getID()) != 64)
138 if (AMDGPU::getRegBitWidth(BaseRC->getID()) != 64)
lib/Target/AMDGPU/SIFoldOperands.cpp 845 if (UseOp.getSubReg() && AMDGPU::getRegBitWidth(FoldRC->getID()) == 64) {
849 if (AMDGPU::getRegBitWidth(UseRC->getID()) != 64)
lib/Target/AMDGPU/SIInstrInfo.cpp 2129 int NumInsts = AMDGPU::getRegBitWidth(RC->getID()) / 32;
2143 int NumInsts = AMDGPU::getRegBitWidth(RC->getID()) / 32;
lib/Target/AMDGPU/SIRegisterInfo.cpp 638 unsigned NumSubRegs = AMDGPU::getRegBitWidth(RC->getID()) / (EltSize * CHAR_BIT);
1739 switch (RC->getID()) {
lib/Target/ARM/ARMBaseRegisterInfo.cpp 233 switch (Super->getID()) {
269 switch (RC->getID()) {
lib/Target/ARM/ARMRegisterBankInfo.cpp 179 switch (RC.getID()) {
lib/Target/Hexagon/HexagonBitSimplify.cpp 415 switch (RC->getID()) {
910 switch (RC->getID()) {
2226 unsigned SRC = MRI.getRegClass(S)->getID();
2269 if (MRI.getRegClass(SrcR)->getID() == Hexagon::DoubleRegsRegClassID)
2731 if (FRC->getID() == Hexagon::DoubleRegsRegClassID) {
2738 if (FRC->getID() == Hexagon::IntRegsRegClassID) {
2749 if (FRC->getID() == Hexagon::PredRegsRegClassID) {
lib/Target/Hexagon/HexagonBitTracker.cpp 93 unsigned ID = RC.getID();
144 switch (RC.getID()) {
155 dbgs() << "Reg class id: " << RC.getID() << " idx: " << Idx << '\n';
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 780 switch (DRC->getID()) {
lib/Target/Hexagon/HexagonPeephole.cpp 242 if (RC0->getID() == Hexagon::PredRegsRegClassID) {
lib/Target/Hexagon/HexagonRegisterInfo.cpp 77 switch (RC->getID()) {
245 if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID())
245 if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID())
247 bool SmallSrc = SrcRC->getID() == Hexagon::HvxVRRegClass.getID();
247 bool SmallSrc = SrcRC->getID() == Hexagon::HvxVRRegClass.getID();
248 bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID();
248 bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID();
316 switch (RC.getID()) {
lib/Target/Hexagon/HexagonVExtract.cpp 130 unsigned StoreOpc = VecRC.getID() == Hexagon::HvxVRRegClassID
lib/Target/Mips/MipsRegisterBankInfo.cpp 83 switch (RC.getID()) {
lib/Target/Mips/MipsRegisterInfo.cpp 69 switch (RC->getID()) {
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 1192 CurDAG->getTargetConstant(RC->getID(), DL, MVT::i32));
1259 CurDAG->getTargetConstant(RC->getID(), DL,
lib/Target/PowerPC/PPCFastISel.cpp 149 return RC->getID() == PPC::VSFRCRegClassID;
152 return RC->getID() == PPC::VSSRCRegClassID;
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 323 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
lib/Target/PowerPC/PPCRegisterInfo.cpp 422 switch (RC->getID()) {
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 1668 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), DL, MVT::i32);
lib/Target/WebAssembly/WebAssemblyPeephole.cpp 98 switch (RegClass->getID()) {
lib/Target/X86/X86RegisterInfo.cpp 130 switch (Super->getID()) {
265 switch (RC->getID()) {