reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/TargetRegisterInfo.h

  197     return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());

lib/CodeGen/ExecutionDomainFix.cpp

  429   for (unsigned Reg : *RC) {

lib/CodeGen/RegisterScavenging.cpp

  288   for (Register Reg : *RC) {
  300   for (Register Reg : *RC)

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

 7966   TargetRegisterClass::iterator I = RC->begin();

lib/CodeGen/SelectionDAG/TargetLowering.cpp

 4136     for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();

lib/Target/AArch64/AArch64CollectLOH.cpp

  468       for (MCPhysReg Reg : AArch64::GPR32RegClass)
  470       for (MCPhysReg Reg : AArch64::GPR64RegClass)

lib/Target/AArch64/AArch64FalkorHWPFFix.cpp

  750       for (unsigned ScratchReg : AArch64::GPR64RegClass) {

lib/Target/AArch64/AArch64FrameLowering.cpp

  404   for (unsigned Reg : AArch64::GPR64RegClass) {

lib/Target/AArch64/AArch64InstrInfo.cpp

 5027   for (unsigned Reg : AArch64::GPR64RegClass) {
 5354   for (unsigned Reg : AArch64::GPR64RegClass) {

lib/Target/AMDGPU/R600RegisterInfo.cpp

   52   for (TargetRegisterClass::iterator I = R600::R600_AddrRegClass.begin(),

lib/Target/AMDGPU/SIFrameLowering.cpp

   29   return makeArrayRef(AMDGPU::SGPR_128RegClass.begin(),
   35   return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(),
   62     for (unsigned Reg : RC) {
   67     for (unsigned Reg : RC) {

lib/Target/AMDGPU/SIISelLowering.cpp

 1655     = makeArrayRef(AMDGPU::VGPR_32RegClass.begin(), 32);
 1677   ArrayRef<MCPhysReg> ArgSGPRs = makeArrayRef(RC->begin(), 32);
 1926       for (unsigned Reg : AMDGPU::SGPR_32RegClass) {

lib/Target/AMDGPU/SIRegisterInfo.cpp

 1509   for (unsigned Reg : *RC)

lib/Target/ARM/ARMBaseRegisterInfo.cpp

  211   for (unsigned Reg : RC)

lib/Target/Hexagon/HexagonBlockRanges.cpp

  227     for (unsigned R : *RC)
  280     unsigned PReg = *RC.begin();

lib/Target/Hexagon/HexagonCopyToCombine.cpp

  452         for (unsigned Reg : Hexagon::IntRegsRegClass)

lib/Target/Hexagon/HexagonExpandCondsets.cpp

  586       assert(VC->begin() != VC->end() && "Empty register class");
  587       PhysR = *VC->begin();

lib/Target/Hexagon/HexagonInstrInfo.cpp

 1633       for (unsigned PR : Hexagon::PredRegsRegClass) {

lib/Target/Hexagon/RDFRegisters.cpp

   34     for (MCPhysReg R : *RC) {

lib/Target/Mips/MipsISelLowering.cpp

 3895     return std::make_pair(*(RC->begin()), RC);
 3946   return std::make_pair(*(RC->begin() + Reg), RC);

lib/Target/Mips/MipsRegisterInfo.cpp

  183     for (MCPhysReg Reg : Mips::AFGR64RegClass)
  187     for (MCPhysReg Reg : Mips::FGR64RegClass)
  220   for (MCPhysReg Reg : Mips::MSACtrlRegClass)

lib/Target/PowerPC/PPCInstrInfo.cpp

 1577         for (TargetRegisterClass::iterator I = RC->begin(),

lib/Target/PowerPC/PPCRegisterInfo.cpp

  339     for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),

lib/Target/X86/X86FrameLowering.cpp

  186     for (auto CS : AvailableRegs)
 2749   for (auto Candidate : RegClass) {

lib/Target/X86/X86VZeroUpper.cpp

  297       for (TargetRegisterClass::iterator i = RC->begin(), e = RC->end(); i != e;