|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/LiveInterval.h 510 return beginIndex() > Start.getBaseIndex() &&
include/llvm/CodeGen/SlotIndexes.h 524 ((I != MBBIndexEnd() && I->first > index) ||
lib/CodeGen/CalcSpillWeights.cpp 214 if (localSplitArtifact && ((si < *start) || (si > *end)))
lib/CodeGen/InlineSpiller.cpp 1212 MachineInstr *SpillToRm = (CIdx > PIdx) ? CurrentSpill : PrevSpill;
1213 MachineInstr *SpillToKeep = (CIdx > PIdx) ? PrevSpill : CurrentSpill;
lib/CodeGen/InterferenceCache.cpp 228 if (!BI->Last.isValid() || StopI > BI->Last)
245 if (!BI->Last.isValid() || StopI > BI->Last)
254 i && RegMaskSlots[i-1].getDeadSlot() > Limit; --i)
lib/CodeGen/LiveDebugVariables.cpp 1056 if (LStop > LII->end)
1068 if (LStop > LocMapI.stop()) {
1361 while (Stop > MBBEnd) {
lib/CodeGen/LiveInterval.cpp 250 if (End > I->end)
432 if (i->start > j->start) {
437 if (i->end > j->start)
474 if (J->end > I->end) {
491 return I != begin() && (--I)->end > Start;
501 if (I == end() || I->start > O.start)
1181 if (!LastStart.isValid() || LastStart > Seg.start) {
1206 assert(ReadI == E || ReadI->end > Seg.start);
1268 if (Src != B && Src[-1].start > SpillSrc[-1].start)
lib/CodeGen/LiveIntervalUnion.cpp 145 while (LRI->start < LiveUnionI.stop() && LRI->end > LiveUnionI.start()) {
lib/CodeGen/LiveIntervals.cpp 1414 if (InstSlot > LastUse && InstSlot < OldIdx)
lib/CodeGen/LiveRangeCalc.cpp 317 if (Seg.end > Begin) {
lib/CodeGen/MachineVerifier.cpp 345 assert(!Last.isValid() || I->first > Last);
830 if (!(idx > lastIndex)) {
2125 if (!(stop > lastIndex)) {
lib/CodeGen/RegAllocGreedy.cpp 1237 } else if (Intf.last() > BI.LastInstr) {
1240 } else if (Intf.last() > BI.FirstInstr) {
lib/CodeGen/RegAllocPBQP.cpp 276 return getStartPoint(I1) > getStartPoint(I2);
287 if (E1 > E2)
lib/CodeGen/RegisterCoalescer.cpp 703 if (BI->start <= ASeg.start && BI->end > ASeg.start)
705 if (BI->start > ASeg.start && BI->start < ASeg.end)
3162 if (I->start > Def)
lib/CodeGen/RegisterPressure.cpp 211 if (BottomIdx > PrevBottom)
lib/CodeGen/SplitKit.cpp 1613 assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) && "Impossible intf");
1662 LeaveBefore.getBaseIndex() > EnterAfter.getBoundaryIndex())) {
1716 assert((!LeaveBefore || LeaveBefore > Start) && "Bad interference");
1732 if (!LeaveBefore || LeaveBefore > BI.LastInstr.getBoundaryIndex()) {
lib/CodeGen/VirtRegMap.cpp 281 if (!Last.isValid() || SR.segments.back().end > Last)
lib/Target/AMDGPU/SIWholeQuadMode.cpp 605 if (Next > LastIdx)