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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc49351 && MI.getOperand(1).getReg() != 0
49353 && MI.getOperand(3).getReg() != 0
gen/lib/Target/X86/X86GenSubtargetInfo.inc22435 && MI->getOperand(1).getReg() != X86::AX
22436 && MI->getOperand(1).getReg() != X86::EAX
22437 && MI->getOperand(1).getReg() != X86::RAX
include/llvm/CodeGen/VirtRegMap.h 97 return getPhys(virtReg) != NO_PHYS_REG;
115 assert(Virt2PhysMap[virtReg.id()] != NO_PHYS_REG &&
161 Virt2PhysMap[virtReg.id()] != NO_PHYS_REG);
lib/CodeGen/RegAllocFast.cpp 650 if (Reg != 0)
lib/CodeGen/RegisterScavenging.cpp 473 if (Scavenged[I].Reg != 0)
544 if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&
lib/CodeGen/SplitKit.cpp 1377 LaneBitmask LM = Sub != 0 ? TRI.getSubRegIndexLaneMask(Sub)
lib/CodeGen/VirtRegMap.cpp 323 assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register.");
519 assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
lib/Target/AArch64/AArch64A53Fix835769.cpp 69 return MI->getOperand(3).getReg() != AArch64::XZR;
lib/Target/AArch64/AArch64FrameLowering.cpp 635 assert(MBBI->getOperand(0).getReg() != AArch64::SP);
739 assert(MI.getOperand(0).getReg() != AArch64::SP);
lib/Target/AArch64/AArch64InstrInfo.cpp 5140 Base->getReg() != AArch64::SP)
5511 (Base->isReg() && Base->getReg() != AArch64::SP))
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp 369 if (Src.first->getReg() != R600::ALU_LITERAL_X)
lib/Target/AMDGPU/R600EmitClauseMarkers.cpp 143 if (Consts[i].first->getReg() != R600::ALU_CONST)
174 if (Consts[i].first->getReg() != R600::ALU_CONST)
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 708 Src0.getReg() != AMDGPU::M0) &&
710 Src1.getReg() != AMDGPU::M0)) {
lib/Target/AMDGPU/SIISelLowering.cpp 3345 assert(Idx->getReg() != AMDGPU::NoRegister);
lib/Target/AMDGPU/SIInstrInfo.cpp 3346 if (!Dst.isReg() || Dst.getReg() != AMDGPU::VCC) {
3500 if (MO.isReg() && MO.getReg() != AMDGPU::M0) {
3627 if (Soff && Soff->getReg() != AMDGPU::M0) {
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 957 if (SDst && (SDst->getReg() != AMDGPU::VCC &&
958 SDst->getReg() != AMDGPU::VCC_LO))
lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp 153 assert(PhysReg != 0);
lib/Target/AMDGPU/SIRegisterInfo.cpp 703 if (TmpReg != AMDGPU::NoRegister) {
727 if (!IsStore && TmpReg != AMDGPU::NoRegister)
772 assert(SuperReg != AMDGPU::M0 && "m0 should never spill");
883 assert(SuperReg != AMDGPU::M0 && "m0 should never spill");
lib/Target/ARM/ARMAsmPrinter.cpp 1205 if (DstReg == FramePtr && FramePtr != ARM::SP)
lib/Target/ARM/ARMBaseInstrInfo.cpp 570 return Offset.getReg() != 0;
584 return (isSub && Offset.getReg() != 0);
687 if (MO.getReg() != ARM::CPSR)
3063 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
lib/Target/ARM/ARMFastISel.cpp 1967 assert(Arg != 0 && "Failed to emit a sext");
1976 assert(Arg != 0 && "Failed to emit a zext");
lib/Target/ARM/ARMFeatures.h 78 return Instr->getOperand(2).getReg() != ARM::PC;
83 return Instr->getOperand(0).getReg() != ARM::PC;
85 return Instr->getOperand(0).getReg() != ARM::PC &&
86 Instr->getOperand(2).getReg() != ARM::PC;
89 return Instr->getOperand(0).getReg() != ARM::PC &&
90 Instr->getOperand(1).getReg() != ARM::PC;
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 1944 if (MO.getReg() != ARM::LR)
lib/Target/ARM/Thumb1FrameLowering.cpp 758 MO.getReg() != ARM::PC) {
lib/Target/ARM/Thumb2InstrInfo.cpp 556 if (OffsetReg != 0) {
lib/Target/ARM/Thumb2SizeReduction.cpp 528 if (BaseReg != ARM::SP)
629 if (MI->getOperand(1).getReg() != ARM::SP) {
977 if (MO.getReg() != ARM::CPSR)
992 if (MO.getReg() != ARM::CPSR)
lib/Target/AVR/AVRExpandPseudoInsts.cpp 876 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
lib/Target/AVR/AVRRegisterInfo.cpp 162 assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer");
lib/Target/Hexagon/HexagonInstrInfo.cpp 3389 if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3389 if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 1213 if (R != Hexagon::USR_OVF && DeadDefs[R])
lib/Target/Lanai/LanaiInstrInfo.cpp 364 if (!MO.isReg() || MO.getReg() != Lanai::SR)
lib/Target/MSP430/MSP430AsmPrinter.cpp 120 if (Base.getReg() != MSP430::SR && Base.getReg() != MSP430::PC) {
120 if (Base.getReg() != MSP430::SR && Base.getReg() != MSP430::PC) {
lib/Target/Mips/Mips16InstrInfo.cpp 360 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
lib/Target/PowerPC/PPCInstrInfo.cpp 3472 if (MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO &&
3473 MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO8)
lib/Target/PowerPC/PPCRegisterInfo.cpp 667 if (SrcReg != PPC::CR0) {
712 if (DestReg != PPC::CR0) {
lib/Target/RISCV/RISCVISelLowering.cpp 2613 if (XRegFromAlias != RISCV::NoRegister)
2659 if (FReg.first != RISCV::NoRegister)
lib/Target/Sparc/DelaySlotFiller.cpp 417 && OrMI->getOperand(1).getReg() != SP::G0
418 && OrMI->getOperand(2).getReg() != SP::G0)
422 && OrMI->getOperand(1).getReg() != SP::G0
lib/Target/Sparc/SparcAsmPrinter.cpp 176 assert(MO.getReg() != SP::O7 &&
lib/Target/X86/X86AsmPrinter.cpp 283 bool HasBaseReg = BaseReg.getReg() != 0;
310 assert(IndexReg.getReg() != X86::ESP &&
lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp 318 if (!((Base.isReg() && Base.getReg() != X86::NoRegister) || Base.isFI()))
lib/Target/X86/X86CallFrameOptimization.cpp 431 (I->getOperand(X86::AddrIndexReg).getReg() != X86::NoRegister) ||
432 (I->getOperand(X86::AddrSegmentReg).getReg() != X86::NoRegister) ||
lib/Target/X86/X86FixupLEAs.cpp 307 Index.getReg() != X86::NoRegister;
363 if (Segment.getReg() != 0 || !Disp.isImm() || Scale.getImm() > 1 ||
377 if (BaseReg != 0)
379 if (IndexReg != 0)
387 if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 &&
387 if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 &&
451 if (p.isReg() && p.getReg() != X86::ESP) {
455 if (q.isReg() && q.getReg() != X86::ESP) {
492 if (Segment.getReg() != 0 || !Offset.isImm() ||
506 if (SrcR1 != 0 && SrcR2 != 0) {
506 if (SrcR1 != 0 && SrcR2 != 0) {
544 Segment.getReg() != X86::NoRegister)
552 if (BaseReg != 0)
554 if (IndexReg != 0)
lib/Target/X86/X86FrameLowering.cpp 220 if (Reg != X86::EFLAGS)
lib/Target/X86/X86InstrInfo.cpp 965 if (ImplicitOp.getReg() != 0)
997 if (ImplicitOp.getReg() != 0)
1019 if (ImplicitOp.getReg() != 0)
1060 if (ImplicitOp.getReg() != 0)
1062 if (ImplicitOp2.getReg() != 0)
1103 if (ImplicitOp.getReg() != 0)
1144 if (ImplicitOp.getReg() != 0)
3212 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
7586 else if ((Op1.isReg() && Op1.getReg() != X86::NoRegister &&
7588 (Op2.getReg() != X86::NoRegister &&
7596 if ((Op1.isReg() && Op1.getReg() != X86::NoRegister)) {
7606 if (Op && Op2.getReg() != X86::NoRegister) {
7619 assert(Op2.getReg() != X86::NoRegister);
7624 assert(Op2.getReg() != X86::NoRegister);
7630 if (((Op1.isReg() && Op1.getReg() != X86::NoRegister) || Op1.isFI()) &&
7631 Op2.getReg() != X86::NoRegister) {
lib/Target/X86/X86MCInstLower.cpp 1172 if (DefRegister != X86::NoRegister)
lib/Target/X86/X86RegisterInfo.cpp 684 MI.getOperand(3).getReg() != X86::NoRegister ||
686 MI.getOperand(5).getReg() != X86::NoRegister)
lib/Target/X86/X86SpeculativeLoadHardening.cpp 1720 if (!BaseMO.isFI() && BaseMO.getReg() != X86::RIP &&
1721 BaseMO.getReg() != X86::NoRegister)
1723 if (IndexMO.getReg() != X86::NoRegister)
1992 if (IndexMO.getReg() != X86::NoRegister &&