reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/MachineInstr.h
  463     assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate &&
include/llvm/CodeGen/MachineInstrBuilder.h
  284     switch (Disp.getType()) {
include/llvm/CodeGen/MachineOperand.h
  962     if (LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
  964         LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
  966       return LHS.getType() == RHS.getType();
  966       return LHS.getType() == RHS.getType();
lib/CodeGen/BranchFolding.cpp
  265     switch (Op.getType()) {
  290     Hash += ((OperandHash << 3) | Op.getType()) << (i & 31);
lib/CodeGen/MIRPrinter.cpp
  823   switch (Op.getType()) {
lib/CodeGen/MachineInstr.cpp
  228   bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata ||
  229                    Op.getType() == MachineOperand::MO_MCSymbol;
lib/CodeGen/MachineOperand.cpp
  275   if (getType() != Other.getType() ||
  275   if (getType() != Other.getType() ||
  279   switch (getType()) {
  344   switch (MO.getType()) {
  347     return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
  349     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
  351     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
  353     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
  355     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
  357     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
  360     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
  363     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
  365     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
  368     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
  371     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
  375     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
  377     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
  379     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
  381     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
  383     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
  385     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
  387     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
  749   switch (getType()) {
lib/CodeGen/MachineScheduler.cpp
 1478       if (BaseOp->getType() != RHS.BaseOp->getType())
 1478       if (BaseOp->getType() != RHS.BaseOp->getType())
 1479         return BaseOp->getType() < RHS.BaseOp->getType();
 1479         return BaseOp->getType() < RHS.BaseOp->getType();
lib/CodeGen/MachineVerifier.cpp
 1645   switch (MO->getType()) {
lib/Target/AArch64/AArch64AsmPrinter.cpp
  501   switch (MO.getType()) {
lib/Target/AArch64/AArch64CollectLOH.cpp
  162   switch (MI.getOperand(2).getType()) {
  187     switch (MI.getOperand(2).getType()) {
lib/Target/AArch64/AArch64InstrInfo.cpp
 2331   if (BaseOp1.getType() != BaseOp2.getType())
 2331   if (BaseOp1.getType() != BaseOp2.getType())
lib/Target/AArch64/AArch64MCInstLower.cpp
  254   switch (MO.getType()) {
lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
  128   switch (MO.getType()) {
lib/Target/AMDGPU/SIFoldOperands.cpp
   47     Kind(FoldOp->getType()),
lib/Target/AMDGPU/SIInstrInfo.cpp
 2893   switch (MO.getType()) {
 2911   if (Op0.getType() != Op1.getType())
 2911   if (Op0.getType() != Op1.getType())
 2914   switch (Op0.getType()) {
lib/Target/ARC/ARCMCInstLower.cpp
   78   MachineOperandType MOTy = MO.getType();
lib/Target/ARM/ARMAsmPrinter.cpp
  203   switch (MO.getType()) {
lib/Target/ARM/ARMExpandPseudoInsts.cpp
  787   switch (MO.getType()) {
  883   switch (MO.getType()) {
lib/Target/ARM/ARMMCInstLower.cpp
   74   switch (MO.getType()) {
lib/Target/AVR/AVRAsmPrinter.cpp
   64   switch (MO.getType()) {
lib/Target/AVR/AVRExpandPseudoInsts.cpp
  289   switch (MI.getOperand(2).getType()) {
  500   switch (MI.getOperand(1).getType()) {
  549   switch (MI.getOperand(1).getType()) {
  981   switch (MI.getOperand(0).getType()) {
lib/Target/AVR/AVRMCInstLower.cpp
   68     switch (MO.getType()) {
lib/Target/BPF/BPFAsmPrinter.cpp
   76   switch (MO.getType()) {
lib/Target/BPF/BPFMCInstLower.cpp
   54     switch (MO.getType()) {
lib/Target/Hexagon/HexagonAsmPrinter.cpp
   79   switch (MO.getType()) {
lib/Target/Hexagon/HexagonConstExtenders.cpp
  713   Kind = Op.getType();
lib/Target/Hexagon/HexagonExpandCondsets.cpp
  602   switch (SO.getType()) {
lib/Target/Hexagon/HexagonMCInstLower.cpp
  117     switch (MO.getType()) {
lib/Target/Lanai/LanaiAsmPrinter.cpp
   68   switch (MO.getType()) {
lib/Target/Lanai/LanaiMCInstLower.cpp
  100     switch (MO.getType()) {
lib/Target/Lanai/LanaiMemAluCombiner.cpp
  171   if (Op1.getType() != Op2.getType())
  171   if (Op1.getType() != Op2.getType())
  174   switch (Op1.getType()) {
lib/Target/MSP430/MSP430AsmPrinter.cpp
   81   switch (MO.getType()) {
lib/Target/MSP430/MSP430MCInstLower.cpp
  122     switch (MO.getType()) {
lib/Target/Mips/MipsAsmPrinter.cpp
  526       if ((MO.getType()) != MachineOperand::MO_Immediate)
  531       if ((MO.getType()) != MachineOperand::MO_Immediate)
  536       if ((MO.getType()) != MachineOperand::MO_Immediate)
  541       if ((MO.getType()) != MachineOperand::MO_Immediate)
  546       if ((MO.getType()) != MachineOperand::MO_Immediate)
  554       if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) {
  682   switch (MO.getType()) {
lib/Target/Mips/MipsMCInstLower.cpp
  181   MachineOperandType MOTy = MO.getType();
lib/Target/NVPTX/NVPTXAsmPrinter.cpp
  241   switch (MO.getType()) {
 2211   switch (MO.getType()) {
lib/Target/PowerPC/PPCAsmPrinter.cpp
  210   switch (MO.getType()) {
  242     O << "<unknown operand type: " << (unsigned)MO.getType() << ">";
  519   switch (MO.getType()) {
lib/Target/PowerPC/PPCMCInstLower.cpp
  165   switch (MO.getType()) {
lib/Target/RISCV/RISCVAsmPrinter.cpp
  111   switch (MO.getType()) {
lib/Target/RISCV/RISCVMCInstLower.cpp
   92   switch (MO.getType()) {
lib/Target/RISCV/RISCVMergeBaseOffset.cpp
   84       HiLUI.getOperand(1).getType() != MachineOperand::MO_GlobalAddress ||
   92       LoADDI->getOperand(2).getType() != MachineOperand::MO_GlobalAddress ||
lib/Target/Sparc/SparcAsmPrinter.cpp
  349   switch (MO.getType()) {
lib/Target/Sparc/SparcMCInstLower.cpp
   37   switch(MO.getType()) {
   70   switch(MO.getType()) {
lib/Target/SystemZ/SystemZMCInstLower.cpp
   40   switch (MO.getType()) {
   80   switch (MO.getType()) {
lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
  376     switch (MO.getType()) {
lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
  215     switch (MO.getType()) {
lib/Target/X86/X86AsmPrinter.cpp
  113   switch (MO.getType()) {
  206   switch (MO.getType()) {
  241   if (!Modifier || MO.getType() != MachineOperand::MO_Register)
  261   switch (MO.getType()) {
  291   switch (DispSpec.getType()) {
  446       switch (MO.getType()) {
  469       switch (MO.getType()) {
lib/Target/X86/X86MCInstLower.cpp
  400   switch (MO.getType()) {
 1110     switch (CallTarget.getType()) {
 1263     switch (CalleeMO.getType()) {
lib/Target/X86/X86OptimizeLEAs.cpp
  144     switch (Val.Disp->getType()) {
lib/Target/XCore/XCoreAsmPrinter.cpp
  206   switch (MO.getType()) {
lib/Target/XCore/XCoreMCInstLower.cpp
   79   MachineOperandType MOTy = MO.getType();