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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc113224 /*252108*/ /*SwitchOpcode*/ 76, TARGET_VAL(ISD::UMIN),// ->252187
gen/lib/Target/AArch64/AArch64GenFastISel.inc 7745 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc28053 /* 58837*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
28112 /* 58946*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
56192 /*122944*/ /*SwitchOpcode*/ 97|128,9/*1249*/, TARGET_VAL(ISD::UMIN),// ->124197
56205 /*122970*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
56248 /*123059*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
56276 /*123110*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
56307 /*123164*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
56336 /*123216*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
56388 /*123310*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
56443 /*123410*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
56465 /*123460*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
56505 /*123555*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
56548 /*123653*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
56590 /*123751*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
56659 /*123914*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
56781 /*124205*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
56788 /*124217*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
56931 /*124482*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
56982 /*124575*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
57026 /*124657*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
57185 /*125017*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
57253 /*125179*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
59939 /*131105*/ /*SwitchOpcode*/ 61, TARGET_VAL(ISD::UMIN),// ->131169
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 7789 /* 29724*/ /*SwitchOpcode*/ 104, TARGET_VAL(ISD::UMIN),// ->29831
gen/lib/Target/ARM/ARMGenDAGISel.inc52705 /*117615*/ /*SwitchOpcode*/ 83|128,1/*211*/, TARGET_VAL(ISD::UMIN),// ->117830
gen/lib/Target/ARM/ARMGenFastISel.inc 5187 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/Mips/MipsGenDAGISel.inc28616 /* 54113*/ /*SwitchOpcode*/ 32|128,1/*160*/, TARGET_VAL(ISD::UMIN),// ->54277
gen/lib/Target/Mips/MipsGenFastISel.inc 3430 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc58355 /*123960*/ /*SwitchOpcode*/ 81, TARGET_VAL(ISD::UMIN),// ->124044
gen/lib/Target/PowerPC/PPCGenDAGISel.inc42828 /*107377*/ /*SwitchOpcode*/ 74, TARGET_VAL(ISD::UMIN),// ->107454
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3257 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc78938 /*165903*/ /*SwitchOpcode*/ 117|128,1/*245*/, TARGET_VAL(ISD::UMIN),// ->166152
83988 /*175977*/ /*SwitchOpcode*/ 117|128,1/*245*/, TARGET_VAL(ISD::UMIN),// ->176226
88865 /*185534*/ /*SwitchOpcode*/ 14|128,2/*270*/, TARGET_VAL(ISD::UMIN),// ->185808
95119 /*198060*/ /*SwitchOpcode*/ 10|128,2/*266*/, TARGET_VAL(ISD::UMIN),// ->198330
101860 /*211474*/ /*SwitchOpcode*/ 56|128,2/*312*/, TARGET_VAL(ISD::UMIN),// ->211790
109182 /*226298*/ /*SwitchOpcode*/ 54|128,2/*310*/, TARGET_VAL(ISD::UMIN),// ->226612
115691 /*239346*/ /*SwitchOpcode*/ 52|128,2/*308*/, TARGET_VAL(ISD::UMIN),// ->239658
119197 /*246095*/ /*SwitchOpcode*/ 32|128,1/*160*/, TARGET_VAL(ISD::UMIN),// ->246259
121891 /*251477*/ /*SwitchOpcode*/ 126|128,1/*254*/, TARGET_VAL(ISD::UMIN),// ->251735
124480 /*256346*/ /*SwitchOpcode*/ 47, TARGET_VAL(ISD::UMIN),// ->256396
126901 /*260931*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::UMIN),// ->260982
145681 /*298057*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMIN),
147594 /*301634*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::UMIN),// ->301685
159566 /*324285*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::UMIN),// ->324322
161294 /*327527*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::UMIN),// ->327564
177379 /*359643*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::UMIN),// ->359665
178324 /*361340*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::UMIN),// ->361361
187340 /*378618*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::UMIN),// ->378655
188105 /*380075*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::UMIN),// ->380112
188743 /*381285*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::UMIN),// ->381307
189055 /*381861*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::UMIN),// ->381882
214642 /*435621*/ /*SwitchOpcode*/ 37|128,14/*1829*/, TARGET_VAL(ISD::UMIN),// ->437454
gen/lib/Target/X86/X86GenFastISel.inc13533 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
include/llvm/CodeGen/TargetLowering.h 2264 case ISD::UMIN:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1526 case ISD::UMIN:
4234 case ISD::SMIN: AltOpcode = ISD::UMIN; break;
4236 case ISD::UMIN: AltOpcode = ISD::SMIN; break;
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3090 case ISD::UMIN:
3099 case ISD::UMIN: Pred = ISD::SETULT; break;
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 81 case ISD::UMIN:
711 return DAG.getNode(ISD::UMIN, dl, PromotedType, Add, SatMax);
1760 case ISD::UMIN:
2086 return std::make_pair(ISD::SETLT, ISD::UMIN);
2087 case ISD::UMIN:
2088 return std::make_pair(ISD::SETULT, ISD::UMIN);
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 437 case ISD::UMIN:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 122 case ISD::UMIN:
956 case ISD::UMIN:
2132 case ISD::VECREDUCE_UMIN: CombineOpc = ISD::UMIN; break;
2746 case ISD::UMIN:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 3242 case ISD::UMIN: {
3629 case ISD::UMIN:
4710 case ISD::UMIN: return std::make_pair(C1.ule(C2) ? C1 : C2, true);
5109 case ISD::UMIN:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 3289 case SPF_UMIN: Opc = ISD::UMIN; break;
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 266 case ISD::UMIN: return "umin";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 6789 return DAG.getNode(ISD::UMIN, dl, IdxVT, Idx,
6898 if (Opcode == ISD::UADDSAT && isOperationLegalOrCustom(ISD::UMIN, VT)) {
6900 SDValue Min = DAG.getNode(ISD::UMIN, dl, VT, LHS, InvRHS);
7331 case ISD::VECREDUCE_UMIN: BaseOpcode = ISD::UMIN; break;
lib/CodeGen/TargetLoweringBase.cpp 644 setOperationAction(ISD::UMIN, VT, Expand);
lib/Target/AArch64/AArch64ISelLowering.cpp 877 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
2852 return DAG.getNode(ISD::UMIN, dl, Op.getValueType(),
12080 ReplaceReductionResults(N, Results, DAG, ISD::UMIN, AArch64ISD::UMINV);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 347 setOperationAction(ISD::UMIN, MVT::i32, Legal);
lib/Target/AMDGPU/SIISelLowering.cpp 438 setOperationAction(ISD::UMIN, MVT::i16, Legal);
605 setOperationAction(ISD::UMIN, MVT::v2i16, Legal);
633 setOperationAction(ISD::UMIN, MVT::v4i16, Custom);
713 setTargetDAGCombine(ISD::UMIN);
4075 case ISD::UMIN:
9004 case ISD::UMIN:
9163 if (Opc == ISD::UMIN && Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) {
9287 case ISD::UMIN:
9960 case ISD::UMIN:
lib/Target/ARM/ARMISelLowering.cpp 210 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
258 setOperationAction(ISD::UMIN, VT, Legal);
3723 ? ISD::UMIN : ISD::UMAX;
lib/Target/Mips/MipsSEISelLowering.cpp 349 setOperationAction(ISD::UMIN, Ty, Legal);
2039 return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0),
2051 return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0),
lib/Target/NVPTX/NVPTXISelLowering.cpp 498 setOperationAction(ISD::UMIN, Ty, Legal);
lib/Target/PowerPC/PPCISelLowering.cpp 572 setOperationAction(ISD::UMIN, VT, Legal);
578 setOperationAction(ISD::UMIN, VT, Expand);
673 setOperationAction(ISD::UMIN, MVT::v2i64, Expand);
lib/Target/X86/X86ISelLowering.cpp 876 setOperationAction(ISD::UMIN, VT, VT == MVT::v16i8 ? Legal : Custom);
1045 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
1046 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
1208 setOperationAction(ISD::UMIN, MVT::v4i64, Custom);
1224 setOperationAction(ISD::UMIN, VT, HasInt256 ? Legal : Custom);
1453 setOperationAction(ISD::UMIN, VT, Legal);
1547 setOperationAction(ISD::UMIN, VT, Legal);
1681 setOperationAction(ISD::UMIN, VT, Legal);
20803 TLI.isOperationLegal(ISD::UMIN, VT)) {
20825 case ISD::SETULE: Opc = ISD::UMIN; break;
24923 if (Opcode == ISD::UADDSAT && !TLI.isOperationLegal(ISD::UMIN, VT)) {
24994 assert((Opcode == ISD::UMIN || Opcode == ISD::UMAX) &&
24999 Opcode = (Opcode == ISD::UMIN ? ISD::SMIN : ISD::SMAX);
25009 case ISD::UMIN: CC = ISD::CondCode::SETULT; break;
27773 case ISD::UMIN: return LowerMINMAX(Op, DAG);
35758 Extract, BinOp, {ISD::SMAX, ISD::SMIN, ISD::UMAX, ISD::UMIN}, true);
35806 MinPos = DAG.getNode(ISD::UMIN, DL, SrcVT, MinPos, Upper);
39897 if (SDValue UMin = MatchMinMax(In, ISD::UMIN, C2))
44149 } else if (Op1.getOpcode() == ISD::UMIN) {
44192 SDValue UMin = DAG.getNode(ISD::UMIN, SDLoc(SubusLHS), ExtType, SubusRHS,
lib/Target/X86/X86TargetTransformInfo.cpp 2691 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN;
2708 {ISD::UMIN, MVT::v2i64, 8},
2710 {ISD::UMIN, MVT::v4i32, 8},
2712 {ISD::UMIN, MVT::v8i16, 6},
2714 {ISD::UMIN, MVT::v16i8, 6},
2720 {ISD::UMIN, MVT::v2i64,10},
2722 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8"
2724 {ISD::UMIN, MVT::v8i16, 2},
2726 {ISD::UMIN, MVT::v16i8, 3},
2731 {ISD::UMIN, MVT::v2i64, 8}, // The data reported by the IACA is "8.6"
2739 {ISD::UMIN, MVT::v2i64, 3},
2741 {ISD::UMIN, MVT::v4i32, 1},
2743 {ISD::UMIN, MVT::v8i16, 1},
2745 {ISD::UMIN, MVT::v16i8, 2},
2747 {ISD::UMIN, MVT::v4i64, 7},
2749 {ISD::UMIN, MVT::v8i32, 3},
2751 {ISD::UMIN, MVT::v16i16, 3},
2753 {ISD::UMIN, MVT::v32i8, 3},
2758 {ISD::UMIN, MVT::v4i64, 2},
2760 {ISD::UMIN, MVT::v8i32, 1},
2762 {ISD::UMIN, MVT::v16i16, 1},
2764 {ISD::UMIN, MVT::v32i8, 2},
2771 {ISD::UMIN, MVT::v8i64, 2},
2773 {ISD::UMIN, MVT::v16i32, 1},
2783 {ISD::UMIN, MVT::v2i64, 8},
2785 {ISD::UMIN, MVT::v4i32, 8},
2787 {ISD::UMIN, MVT::v8i16, 6},
2789 {ISD::UMIN, MVT::v16i8, 6},
2795 {ISD::UMIN, MVT::v2i64,11},
2797 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8"
2799 {ISD::UMIN, MVT::v8i16, 2}, // The data reported by the IACA is "1.8"
2801 {ISD::UMIN, MVT::v16i8, 3},
2806 {ISD::UMIN, MVT::v2i64, 9}, // The data reported by the IACA is "8.6"
2814 {ISD::UMIN, MVT::v2i64, 3},
2816 {ISD::UMIN, MVT::v4i32, 1},
2818 {ISD::UMIN, MVT::v8i16, 1},
2820 {ISD::UMIN, MVT::v16i8, 2},
2822 {ISD::UMIN, MVT::v4i64, 7},
2824 {ISD::UMIN, MVT::v8i32, 2},
2826 {ISD::UMIN, MVT::v16i16, 2},
2828 {ISD::UMIN, MVT::v32i8, 2},
2833 {ISD::UMIN, MVT::v4i64, 1},
2835 {ISD::UMIN, MVT::v8i32, 1},
2837 {ISD::UMIN, MVT::v16i16, 1},
2839 {ISD::UMIN, MVT::v32i8, 1},
2846 {ISD::UMIN, MVT::v8i64, 1},
2848 {ISD::UMIN, MVT::v16i32, 1},