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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc86674 /*200128*/ /*SwitchOpcode*/ 31|128,20/*2591*/, TARGET_VAL(ISD::SUB),// ->202723
88541 /*203792*/ OPC_SwitchOpcode /*2 cases */, 96, TARGET_VAL(ISD::SUB),// ->203892
88605 /*203903*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
88654 /*203986*/ OPC_SwitchOpcode /*2 cases */, 116, TARGET_VAL(ISD::SUB),// ->204106
88730 /*204116*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
92592 /*210785*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
92613 /*210826*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
93062 /*211748*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
93089 /*211800*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
99529 /*224169*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
99744 /*224551*/ /*SwitchOpcode*/ 56, TARGET_VAL(ISD::SUB),// ->224610
108262 /*241717*/ /*SwitchOpcode*/ 107, TARGET_VAL(ISD::SUB),// ->241827
gen/lib/Target/AArch64/AArch64GenFastISel.inc 7742 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc27981 /* 58690*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
27986 /* 58699*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
28013 /* 58747*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
28018 /* 58756*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
28046 /* 58826*/ /*SwitchOpcode*/ 102, TARGET_VAL(ISD::SUB),// ->58931
28105 /* 58935*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
47720 /*102787*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
47728 /*102800*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
47819 /*102989*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
47827 /*103002*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
52739 /*114456*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
52759 /*114506*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
56118 /*122781*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
56129 /*122801*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
59511 /*130185*/ /*SwitchOpcode*/ 56|128,1/*184*/, TARGET_VAL(ISD::SUB),// ->130373
59861 /*130913*/ /*SwitchOpcode*/ 61, TARGET_VAL(ISD::SUB),// ->130977
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 63 /* 14*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
71 /* 27*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
161 /* 373*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
169 /* 386*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
474 /* 1463*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
511 /* 1606*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
7681 /* 29296*/ /*SwitchOpcode*/ 104, TARGET_VAL(ISD::SUB),// ->29403
gen/lib/Target/ARC/ARCGenDAGISel.inc 523 /* 855*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::SUB),// ->906
gen/lib/Target/ARM/ARMGenDAGISel.inc25782 /* 55645*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
25796 /* 55678*/ OPC_SwitchOpcode /*3 cases */, 30, TARGET_VAL(ISD::SUB),// ->55712
25903 /* 55930*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
25928 /* 55988*/ OPC_SwitchOpcode /*3 cases */, 55, TARGET_VAL(ISD::SUB),// ->56047
26166 /* 56502*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
26198 /* 56571*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
26414 /* 57041*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
26431 /* 57073*/ OPC_SwitchOpcode /*5 cases */, 24, TARGET_VAL(ISD::SUB),// ->57101
30961 /* 68155*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
30980 /* 68186*/ OPC_SwitchOpcode /*2 cases */, 65, TARGET_VAL(ISD::SUB),// ->68255
30993 /* 68210*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
31018 /* 68259*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
31031 /* 68281*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
31055 /* 68329*/ OPC_SwitchOpcode /*2 cases */, 96, TARGET_VAL(ISD::SUB),// ->68429
31068 /* 68351*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
31088 /* 68385*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
31112 /* 68433*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
31125 /* 68453*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
31143 /* 68484*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
33156 /* 72942*/ /*SwitchOpcode*/ 1|128,19/*2433*/, TARGET_VAL(ISD::SUB),// ->75379
35215 /* 77667*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
46640 /*103469*/ /*SwitchOpcode*/ 81, TARGET_VAL(ISD::SUB),// ->103553
46842 /*103905*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
47553 /*105534*/ /*SwitchOpcode*/ 88, TARGET_VAL(ISD::SUB),// ->105625
47753 /*106017*/ /*SwitchOpcode*/ 88, TARGET_VAL(ISD::SUB),// ->106108
gen/lib/Target/ARM/ARMGenFastISel.inc 5183 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
6369 case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
6724 case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
6771 case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_imm0_4095(VT, RetVT, Op0, Op0IsKill, imm1);
gen/lib/Target/AVR/AVRGenDAGISel.inc 680 /* 1130*/ /*SwitchOpcode*/ 101, TARGET_VAL(ISD::SUB),// ->1234
gen/lib/Target/BPF/BPFGenDAGISel.inc 1396 /* 2404*/ /*SwitchOpcode*/ 92, TARGET_VAL(ISD::SUB),// ->2499
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc 4363 /* 8213*/ /*SwitchOpcode*/ 50|128,53/*6834*/, TARGET_VAL(ISD::SUB),// ->15051
25175 /* 48364*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::SUB),// ->48386
25189 /* 48389*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
25243 /* 48492*/ /*SwitchOpcode*/ 20, TARGET_VAL(ISD::SUB),// ->48515
25259 /* 48519*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
26045 /* 50035*/ /*SwitchOpcode*/ 29|128,8/*1053*/, TARGET_VAL(ISD::SUB),// ->51092
31065 /* 59984*/ /*SwitchOpcode*/ 17, TARGET_VAL(ISD::SUB),// ->60004
65037 /*125061*/ /*SwitchOpcode*/ 17, TARGET_VAL(ISD::SUB),// ->125081
gen/lib/Target/Lanai/LanaiGenDAGISel.inc 664 /* 1150*/ /*SwitchOpcode*/ 73, TARGET_VAL(ISD::SUB),// ->1226
gen/lib/Target/MSP430/MSP430GenDAGISel.inc 1565 /* 3238*/ /*SwitchOpcode*/ 19|128,2/*275*/, TARGET_VAL(ISD::SUB),// ->3517
3972 /* 8000*/ /*SwitchOpcode*/ 22|128,1/*150*/, TARGET_VAL(ISD::SUB),// ->8154
gen/lib/Target/Mips/MipsGenDAGISel.inc16261 /* 30083*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::SUB),// ->30117
18204 /* 34076*/ /*SwitchOpcode*/ 41|128,2/*297*/, TARGET_VAL(ISD::SUB),// ->34377
gen/lib/Target/Mips/MipsGenFastISel.inc 3426 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc54744 /*117702*/ /*SwitchOpcode*/ 12|128,1/*140*/, TARGET_VAL(ISD::SUB),// ->117846
gen/lib/Target/PowerPC/PPCGenDAGISel.inc24246 /* 58818*/ /*SwitchOpcode*/ 85|128,1/*213*/, TARGET_VAL(ISD::SUB),// ->59035
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3254 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 5520 /* 10197*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
11908 /* 22150*/ /*SwitchOpcode*/ 40, TARGET_VAL(ISD::SUB),// ->22193
gen/lib/Target/Sparc/SparcGenDAGISel.inc 2257 /* 4152*/ /*SwitchOpcode*/ 64, TARGET_VAL(ISD::SUB),// ->4219
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc 4236 /* 8392*/ /*SwitchOpcode*/ 68|128,13/*1732*/, TARGET_VAL(ISD::SUB),// ->10128
7655 /* 14810*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
7746 /* 14953*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
7778 /* 15003*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
7810 /* 15053*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
7839 /* 15099*/ /*SwitchOpcode*/ 15|128,1/*143*/, TARGET_VAL(ISD::SUB),// ->15246
7952 /* 15282*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
7965 /* 15303*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::SUB),// ->15333
8003 /* 15364*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
8016 /* 15385*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::SUB),// ->15415
8060 /* 15456*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
8073 /* 15477*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::SUB),// ->15507
8110 /* 15537*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
8123 /* 15558*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::SUB),// ->15588
8150 /* 15602*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
8218 /* 15710*/ /*SwitchOpcode*/ 15|128,1/*143*/, TARGET_VAL(ISD::SUB),// ->15857
8331 /* 15893*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
8344 /* 15914*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::SUB),// ->15944
8382 /* 15975*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
8395 /* 15996*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::SUB),// ->16026
8439 /* 16067*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
8452 /* 16088*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::SUB),// ->16118
8489 /* 16148*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
8502 /* 16169*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::SUB),// ->16199
8529 /* 16213*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
8597 /* 16321*/ /*SwitchOpcode*/ 15|128,1/*143*/, TARGET_VAL(ISD::SUB),// ->16468
8710 /* 16504*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
8723 /* 16525*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::SUB),// ->16555
8761 /* 16586*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
8774 /* 16607*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::SUB),// ->16637
8818 /* 16678*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
8831 /* 16699*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::SUB),// ->16729
8868 /* 16759*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
8881 /* 16780*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::SUB),// ->16810
8908 /* 16824*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
8976 /* 16932*/ /*SwitchOpcode*/ 15|128,1/*143*/, TARGET_VAL(ISD::SUB),// ->17079
9089 /* 17115*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
9102 /* 17136*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::SUB),// ->17166
9140 /* 17197*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
9153 /* 17218*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::SUB),// ->17248
9197 /* 17289*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
9210 /* 17310*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::SUB),// ->17340
9247 /* 17370*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
9260 /* 17391*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::SUB),// ->17421
9304 /* 17464*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
9329 /* 17506*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
9345 /* 17535*/ /*SwitchOpcode*/ 77, TARGET_VAL(ISD::SUB),// ->17615
9411 /* 17645*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
9445 /* 17702*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
9479 /* 17759*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
9518 /* 17826*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
9543 /* 17868*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
9559 /* 17897*/ /*SwitchOpcode*/ 77, TARGET_VAL(ISD::SUB),// ->17977
9620 /* 18001*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
9672 /* 18092*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
9715 /* 18171*/ /*SwitchOpcode*/ 48|128,1/*176*/, TARGET_VAL(ISD::SUB),// ->18351
9835 /* 18385*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
9850 /* 18413*/ /*SwitchOpcode*/ 77, TARGET_VAL(ISD::SUB),// ->18493
9921 /* 18533*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
9946 /* 18575*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
9962 /* 18604*/ /*SwitchOpcode*/ 77, TARGET_VAL(ISD::SUB),// ->18684
10023 /* 18708*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
10075 /* 18799*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
10118 /* 18878*/ /*SwitchOpcode*/ 48|128,1/*176*/, TARGET_VAL(ISD::SUB),// ->19058
10238 /* 19092*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
10253 /* 19120*/ /*SwitchOpcode*/ 77, TARGET_VAL(ISD::SUB),// ->19200
10324 /* 19240*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
10349 /* 19282*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
10365 /* 19311*/ /*SwitchOpcode*/ 77, TARGET_VAL(ISD::SUB),// ->19391
10426 /* 19415*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
10478 /* 19506*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
10521 /* 19585*/ /*SwitchOpcode*/ 48|128,1/*176*/, TARGET_VAL(ISD::SUB),// ->19765
10641 /* 19799*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
10656 /* 19827*/ /*SwitchOpcode*/ 77, TARGET_VAL(ISD::SUB),// ->19907
10727 /* 19947*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
10752 /* 19989*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
10768 /* 20018*/ /*SwitchOpcode*/ 77, TARGET_VAL(ISD::SUB),// ->20098
10829 /* 20122*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
10881 /* 20213*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
10924 /* 20292*/ /*SwitchOpcode*/ 48|128,1/*176*/, TARGET_VAL(ISD::SUB),// ->20472
18075 /* 33587*/ /*SwitchOpcode*/ 33, TARGET_VAL(ISD::SUB),// ->33623
18212 /* 33876*/ /*SwitchOpcode*/ 33, TARGET_VAL(ISD::SUB),// ->33912
18349 /* 34170*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::SUB),// ->34207
18477 /* 34444*/ /*SwitchOpcode*/ 33, TARGET_VAL(ISD::SUB),// ->34480
26773 /* 50908*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
26798 /* 50946*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
26826 /* 50990*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
26852 /* 51030*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
26880 /* 51074*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
26906 /* 51114*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
26934 /* 51158*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
26960 /* 51198*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
26990 /* 51247*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
27012 /* 51282*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
27037 /* 51323*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
27060 /* 51360*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
27085 /* 51401*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
27108 /* 51438*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
27133 /* 51479*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
27156 /* 51516*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
27645 /* 52373*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
27668 /* 52411*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
27690 /* 52447*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
27714 /* 52487*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
27736 /* 52523*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
27760 /* 52563*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
27782 /* 52599*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
27806 /* 52639*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc16680 /* 32346*/ /*SwitchOpcode*/ 3|128,1/*131*/, TARGET_VAL(ISD::SUB),// ->32481
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 1921 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc 2273 /* 4683*/ /*SwitchOpcode*/ 31|128,4/*543*/, TARGET_VAL(ISD::SUB),// ->5230
8902 /* 19207*/ /*SwitchOpcode*/ 15|128,3/*399*/, TARGET_VAL(ISD::SUB),// ->19610
20541 /* 41587*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::SUB),// ->41621
20598 /* 41704*/ /*SwitchOpcode*/ 32, TARGET_VAL(ISD::SUB),// ->41739
36924 /* 77240*/ /*SwitchOpcode*/ 33, TARGET_VAL(ISD::SUB),// ->77276
36964 /* 77326*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::SUB),// ->77363
38475 /* 80566*/ OPC_SwitchOpcode /*2 cases */, 42, TARGET_VAL(ISD::SUB),// ->80612
38533 /* 80696*/ OPC_SwitchOpcode /*2 cases */, 43, TARGET_VAL(ISD::SUB),// ->80743
44152 /* 92372*/ /*SwitchOpcode*/ 98|128,11/*1506*/, TARGET_VAL(ISD::SUB),// ->93882
45252 /* 94728*/ OPC_SwitchOpcode /*2 cases */, 40, TARGET_VAL(ISD::SUB),// ->94772
45307 /* 94851*/ OPC_SwitchOpcode /*2 cases */, 41, TARGET_VAL(ISD::SUB),// ->94896
77787 /*163668*/ /*SwitchOpcode*/ 120, TARGET_VAL(ISD::SUB),// ->163791
82919 /*173759*/ /*SwitchOpcode*/ 120, TARGET_VAL(ISD::SUB),// ->173882
88002 /*183896*/ /*SwitchOpcode*/ 3|128,1/*131*/, TARGET_VAL(ISD::SUB),// ->184031
94330 /*196450*/ /*SwitchOpcode*/ 1|128,1/*129*/, TARGET_VAL(ISD::SUB),// ->196583
100480 /*208849*/ /*SwitchOpcode*/ 24|128,1/*152*/, TARGET_VAL(ISD::SUB),// ->209005
107914 /*223711*/ /*SwitchOpcode*/ 23|128,1/*151*/, TARGET_VAL(ISD::SUB),// ->223866
114616 /*237340*/ /*SwitchOpcode*/ 2|128,1/*130*/, TARGET_VAL(ISD::SUB),// ->237474
118480 /*244762*/ /*SwitchOpcode*/ 66, TARGET_VAL(ISD::SUB),// ->244831
120371 /*248440*/ /*SwitchOpcode*/ 113, TARGET_VAL(ISD::SUB),// ->248556
124166 /*255784*/ /*SwitchOpcode*/ 47, TARGET_VAL(ISD::SUB),// ->255834
126625 /*260378*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::SUB),// ->260429
145302 /*297387*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
147273 /*300988*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::SUB),// ->301039
159427 /*324034*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::SUB),// ->324071
161171 /*327279*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::SUB),// ->327316
177288 /*359489*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::SUB),// ->359511
178247 /*361193*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::SUB),// ->361214
187023 /*378055*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::SUB),// ->378092
187826 /*379522*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::SUB),// ->379559
188584 /*381015*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::SUB),// ->381037
188920 /*381603*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::SUB),// ->381624
gen/lib/Target/X86/X86GenFastISel.inc13530 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
14120 case ISD::SUB: return fastEmit_ISD_SUB_ri(VT, RetVT, Op0, Op0IsKill, imm1);
14246 case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_i64immSExt32(VT, RetVT, Op0, Op0IsKill, imm1);
14351 case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_i16immSExt8(VT, RetVT, Op0, Op0IsKill, imm1);
14455 case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_i32immSExt8(VT, RetVT, Op0, Op0IsKill, imm1);
14559 case ISD::SUB: return fastEmit_ISD_SUB_ri_Predicate_i64immSExt8(VT, RetVT, Op0, Op0IsKill, imm1);
gen/lib/Target/XCore/XCoreGenDAGISel.inc 1204 /* 1964*/ /*SwitchOpcode*/ 98, TARGET_VAL(ISD::SUB),// ->2065
include/llvm/CodeGen/TargetLowering.h 2300 case ISD::SUB:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1494 case ISD::SUB: return visitSUB(N);
1646 case ISD::SUB:
1995 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
2030 return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, C1, LowBit);
2036 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
2114 if (N0.getOpcode() == ISD::SUB &&
2116 SDValue Sub = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, N1.getNode(),
2123 if (N0.getOpcode() == ISD::SUB &&
2128 return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1));
2166 if (N0.getOpcode() == ISD::SUB && isNullOrNullSplat(N0.getOperand(0)))
2167 return DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1));
2170 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0)))
2171 return DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(1));
2174 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
2178 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
2182 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
2182 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
2184 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2188 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
2188 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
2190 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0),
2194 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
2196 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2200 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
2202 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2206 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
2207 N1.getOperand(0).getOpcode() == ISD::SUB &&
2213 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
2213 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
2220 return DAG.getNode(ISD::SUB, DL, VT,
2243 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
2261 return DAG.getNode(ISD::SUB, DL, VT, A, Xor.getOperand(0));
2272 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(1), Not);
2277 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
2414 return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, N0, N1.getOperand(0));
2424 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB &&
2426 return DAG.getNode(ISD::SUB, DL, VT, N0,
2442 return DAG.getNode(ISD::SUB, DL, VT, N1, Not);
2448 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
2451 return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1));
2455 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
2457 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1));
2468 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
2477 return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt);
2876 return DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, N0.getNode(),
2926 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0)))
2930 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
2946 ISD::SUB, DL, VT, N0.getOperand(1).getNode(), N1.getNode());
2956 SDValue NewC = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, N0.getNode(),
2959 return DAG.getNode(ISD::SUB, DL, VT, NewC, N1.getOperand(0));
2964 if (N0.getOpcode() == ISD::SUB &&
2970 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), NewC);
2974 if (N0.getOpcode() == ISD::SUB &&
2978 ISD::SUB, DL, VT, N0.getOperand(0).getNode(), N1.getNode());
2980 return DAG.getNode(ISD::SUB, DL, VT, NewC, N0.getOperand(1));
2985 (N0.getOperand(1).getOpcode() == ISD::SUB ||
2998 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1).getOpcode() == ISD::SUB &&
2998 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1).getOpcode() == ISD::SUB &&
3000 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0),
3004 if (N1.getOpcode() == ISD::SUB && N1.hasOneUse())
3006 DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(1),
3011 if (N1.getOperand(0).getOpcode() == ISD::SUB &&
3018 if (N1.getOperand(1).getOpcode() == ISD::SUB &&
3043 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB && isOneOrOneSplat(N1)) {
3062 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
3068 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(0));
3069 return DAG.getNode(ISD::SUB, DL, VT, Sub, N1.getOperand(1));
3073 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
3075 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
3076 return DAG.getNode(ISD::SUB, DL, VT, Sub, N0.getOperand(1));
3079 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
3082 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), Add);
3152 SDValue NegX = DAG.getNode(ISD::SUB, DL, VT, Zero, X);
3207 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
3238 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
3379 return DAG.getNode(ISD::SUB, DL, VT,
3398 return DAG.getNode(ISD::SUB, DL, VT,
3421 MathOp = ISD::SUB;
3433 R = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), R);
3643 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), N0);
3667 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
3718 SDValue Inexact = DAG.getNode(ISD::SUB, DL, ShiftAmtTy, Bits, C1);
3747 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, Zero, Sra);
3805 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
3936 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
4027 ISD::SUB, DL, VT, DAG.getConstant(NumEltBits, DL, VT), LogBase2);
5266 if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) {
6051 if (Neg.getOpcode() != ISD::SUB)
6961 if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::SUB &&
7266 unsigned CombineOp = SameSide ? ISD::ADD : ISD::SUB;
8705 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1))
8708 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1))
9623 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() &&
9626 TLI.isOperationLegalOrCustom(ISD::SUB, VT)) {
9628 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Zext);
10827 case ISD::SUB:
13480 } else if (N->getOpcode() == ISD::SUB) {
13531 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
13604 Use.getUser()->getOpcode() != ISD::SUB) {
13695 X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1;
13696 Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1;
13700 unsigned Opcode = (Y0 * Y1 < 0) ? ISD::SUB : ISD::ADD;
13765 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
13794 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
13873 (AM == ISD::PRE_INC || AM == ISD::POST_INC ? ISD::ADD : ISD::SUB);
13969 unsigned Opc = IsSub ? ISD::SUB : ISD::ADD;
20253 SDValue LogBase2 = DAG.getNode(ISD::SUB, DL, VT, Base, Ctlz);
lib/CodeGen/SelectionDAG/FastISel.cpp 1798 return selectBinaryOp(I, ISD::SUB);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 1601 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
2868 SDValue Neg = DAG.getNode(ISD::SUB, dl, VT, Zero, And);
3184 case ISD::SUB: {
3212 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3352 unsigned Op = IsAdd ? ISD::ADD : ISD::SUB;
4160 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 299 Mask = DAG.getNode(ISD::SUB, dl, LVT, Mask, DAG.getConstant(1, dl, LVT));
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 130 case ISD::SUB:
438 ISD::SUB, dl, NVT, Op,
703 return DAG.getNode(ISD::SUB, dl, PromotedType, Max, Op2Promoted);
714 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB;
778 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
979 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
1764 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
2015 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
2016 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
2189 RevOpc = ISD::SUB;
2195 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
2235 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
2236 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
2248 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
2316 NoCarryOp = ISD::SUB;
2477 SDValue Neg = DAG.getNode(ISD::SUB, dl, VT,
3092 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 360 case ISD::SUB:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 137 case ISD::SUB:
930 case ISD::SUB:
2738 case ISD::SUB:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 2307 case ISD::SUB:
3044 case ISD::SUB:
3700 case ISD::SUB:
4698 case ISD::SUB: return std::make_pair(C1 - C2, true);
4762 case ISD::SUB: Offset = -uint64_t(Offset); break;
5091 case ISD::SUB:
5376 case ISD::SUB:
5399 case ISD::SUB:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 2366 SDValue SUB = DAG.getNode(ISD::SUB, dl,
2426 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
2571 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, GuardVal);
2626 DAG.getNode(ISD::SUB, dl, VT, SwitchOp, DAG.getConstant(B.First, dl, VT));
4884 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
6255 SDValue NegShAmt = DAG.getNode(ISD::SUB, sdl, VT, Zero, Z);
6262 SDValue NegZ = DAG.getNode(ISD::SUB, sdl, VT, Zero, Z);
6272 SDValue InvShAmt = DAG.getNode(ISD::SUB, sdl, VT, BitWidthC, ShAmt);
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h 676 void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 224 case ISD::SUB: return "sub";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 1920 case ISD::SUB: {
2480 case ISD::SUB:
3012 assert((BOpcode == ISD::ADD || BOpcode == ISD::SUB || BOpcode == ISD::XOR) &&
3076 DAG.getNodeIfExists(ISD::SUB, DAG.getVTList(OpVT), { N1, N0 } ) &&
3077 !DAG.getNodeIfExists(ISD::SUB, DAG.getVTList(OpVT), { N0, N1 } ))
3778 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
3826 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
3850 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
4095 if (OpCode == ISD::ADD || OpCode == ISD::SUB) {
4849 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N0, Q);
5754 SDValue NextSub = DAG.getNode(ISD::SUB, dl, VT, Next,
5758 NextSub = DAG.getNode(ISD::SUB, dl, VT, Next,
5791 !isOperationLegalOrCustom(ISD::SUB, VT) ||
5817 SDValue InvShAmt = DAG.getNode(ISD::SUB, DL, ShVT, BitWidthC, ShAmt);
5849 SDValue Sub = DAG.getNode(ISD::SUB, DL, ShVT, BitWidthC, Op1);
5856 !isOperationLegalOrCustom(ISD::SUB, VT) ||
5870 SDValue NegOp1 = DAG.getNode(ISD::SUB, DL, ShVT, BitWidthC, Op1);
5916 SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
5933 DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
5937 DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
5941 SDValue Ret = DAG.getNode(ISD::SUB, dl, DstVT,
6174 !isOperationLegalOrCustom(ISD::SUB, VT) ||
6192 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
6302 !isOperationLegalOrCustom(ISD::SUB, VT) ||
6313 DAG.getNode(ISD::SUB, dl, VT, Op, DAG.getConstant(1, dl, VT)));
6318 DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(NumBitsPerElt, dl, VT),
6895 return DAG.getNode(ISD::SUB, dl, VT, Max, RHS);
7120 Result = DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, dl,
7138 Result = DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, dl,
lib/CodeGen/TargetLoweringBase.cpp 1594 case Sub: return ISD::SUB;
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 2533 if (ShiftAmt->getOpcode() == ISD::ADD || ShiftAmt->getOpcode() == ISD::SUB) {
2544 else if (ShiftAmt->getOpcode() == ISD::SUB &&
lib/Target/AArch64/AArch64ISelLowering.cpp 589 setTargetDAGCombine(ISD::SUB);
1598 return Op.getOpcode() == ISD::SUB && isNullConstant(Op.getOperand(0)) &&
1716 } else if (RHS.getOpcode() == ISD::SUB) {
2710 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
2721 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5067 } else if (TVal.getOpcode() == ISD::SUB) {
5608 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
5621 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
5663 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
5676 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
8261 RHS = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, dl, VT), RHS);
8329 SP = DAG.getNode(ISD::SUB, dl, MVT::i64, SP, Size);
8344 SP = DAG.getNode(ISD::SUB, dl, MVT::i64, SP, Size);
9307 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
9372 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
9411 N->use_begin()->getOpcode() == ISD::SUB))
9435 AddSubOpc = ISD::SUB;
9445 AddSubOpc = ISD::SUB;
9467 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Res);
11711 return DAG.getNode(ISD::SUB, DL, MVT::i64, Result,
11723 case ISD::SUB:
11861 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
11869 if (Op->getOpcode() == ISD::SUB)
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 1180 } else if (Addr.getOpcode() == ISD::SUB) {
1190 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
1258 } else if (Addr.getOpcode() == ISD::SUB) {
1271 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 375 setOperationAction(ISD::SUB, VT, Expand);
1615 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1698 SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS);
1739 SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi);
1832 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1872 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1887 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1900 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1924 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1938 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
2007 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
2008 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
2067 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
2435 DAG.getNode(ISD::SUB, SL, MVT::i32, K, LZ),
2638 SDValue OneSubExp = DAG.getNode(ISD::SUB, DL, MVT::i32,
lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp 371 case ISD::SUB:
lib/Target/AMDGPU/R600ISelLowering.cpp 484 case ISD::USUBO: return LowerUADDSUBO(Op, DAG, ISD::SUB, AMDGPUISD::BORROW);
801 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
802 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
839 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
840 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
lib/Target/AMDGPU/SIISelLowering.cpp 599 setOperationAction(ISD::SUB, MVT::v2i16, Legal);
628 setOperationAction(ISD::SUB, MVT::v4i16, Custom);
702 setTargetDAGCombine(ISD::SUB);
4071 case ISD::SUB:
9598 (LHSOpc == ISD::SUB && Opc == ISD::SUBCARRY)) {
9942 case ISD::SUB:
lib/Target/ARC/ARCISelDAGToDAG.cpp 91 if (Addr.getOpcode() != ISD::ADD && Addr.getOpcode() != ISD::SUB &&
107 if (Addr.getOpcode() == ISD::SUB)
136 if (Addr.getOpcode() == ISD::SUB)
lib/Target/ARC/ARCISelLowering.cpp 95 setOperationAction(ISD::SUB, MVT::i32, Legal);
lib/Target/ARM/ARMFastISel.cpp 1766 case ISD::SUB:
2849 return SelectBinaryIntOp(I, ISD::SUB);
lib/Target/ARM/ARMISelDAGToDAG.cpp 606 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
630 if (N.getOpcode() == ISD::SUB)
679 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
693 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
719 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
845 if (N.getOpcode() == ISD::SUB) {
1190 if (N.getOpcode() == ISD::SUB || CurDAG->isBaseWithConstantOffset(N)) {
1195 if (N.getOpcode() == ISD::SUB)
1220 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1250 if (N.getOpcode() == ISD::SUB)
1274 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1280 if (N.getOpcode() == ISD::SUB)
1318 if (N.getOpcode() == ISD::SUB || CurDAG->isBaseWithConstantOffset(N)) {
1329 if (N.getOpcode() == ISD::SUB)
lib/Target/ARM/ARMISelLowering.cpp 1416 setTargetDAGCombine(ISD::SUB);
4392 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4397 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4503 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
5804 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5807 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5846 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5852 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5897 SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X);
5906 SDValue Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
5918 return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ);
5933 Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
6068 ISD::SUB, dl, ShiftVT, getZeroVector(ShiftVT, DAG, dl), N->getOperand(1));
6107 ShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
6347 Carry = DAG.getNode(ISD::SUB, DL, MVT::i32,
8403 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
8414 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
8704 Carry = DAG.getNode(ISD::SUB, DL, MVT::i32,
8717 Carry = DAG.getNode(ISD::SUB, DL, MVT::i32,
11669 case ISD::SUB:
11801 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
11804 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
11864 Res = DAG.getNode(ISD::SUB, DL, VT,
11876 Res = DAG.getNode(ISD::SUB, DL, VT,
11890 Res = DAG.getNode(ISD::SUB, DL, VT,
14316 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, LHS, RHS);
14329 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, LHS, RHS);
14335 DAG.getNode(ISD::SUB, dl, MVT::i32,
14424 case ISD::SUB: return PerformSUBCombine(N, DCI);
14829 if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB ||
15127 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
15186 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
15211 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
15984 SDValue Rem = DAG.getNode(ISD::SUB, dl, VT, Dividend, Mul);
16074 SP = DAG.getNode(ISD::SUB, DL, MVT::i32, SP, Size);
lib/Target/AVR/AVRISelDAGToDAG.cpp 79 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
88 if (N.getOpcode() == ISD::SUB) {
239 if (Op->getOpcode() == ISD::ADD || Op->getOpcode() == ISD::SUB) {
lib/Target/AVR/AVRISelLowering.cpp 725 ISD::SUB, DL, N->getValueType(0), N->getOperand(0),
802 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
808 if (Op->getOpcode() == ISD::SUB)
853 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
859 if (Op->getOpcode() == ISD::SUB)
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 598 if (Shl_0.getOpcode() == ISD::SUB) {
944 case ISD::SUB:
lib/Target/Hexagon/HexagonISelLowering.cpp 1420 ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV,
1487 setOperationAction(ISD::SUB, NativeVT, Legal);
2767 SDValue Op = DAG.getNode(ISD::SUB, dl, VTs.VTs[0], {X, Y});
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 80 setOperationAction(ISD::SUB, T, Legal);
149 setOperationAction(ISD::SUB, T, Legal);
716 SDValue SubV = DAG.getNode(ISD::SUB, dl, MVT::i32,
909 SDValue S = DAG.getNode(ISD::SUB, dl, MVT::i32, IdxV, HalfV);
943 SDValue RolV = DAG.getNode(ISD::SUB, dl, MVT::i32,
995 SDValue ByteXdi = DAG.getNode(ISD::SUB, dl, MVT::i32, HwLenV, ByteIdx);
1261 DAG.getNode(ISD::SUB, dl, ResTy, {InpV, Vec1})});
1262 return DAG.getNode(ISD::SUB, dl, ResTy,
lib/Target/Lanai/LanaiAluCode.h 124 case ISD::SUB:
lib/Target/Lanai/LanaiISelLowering.cpp 142 setTargetDAGCombine(ISD::SUB);
964 Res = DAG.getNode(ISD::SUB, DL, VT, Res, Op);
1030 SDValue Sub = DAG.getNode(ISD::SUB, DL, MVT::i32, StackPointer, Size);
1252 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1262 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1306 ISD::SUB, dl, MVT::i32, DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1481 case ISD::SUB:
lib/Target/MSP430/MSP430ISelDAGToDAG.cpp 422 case ISD::SUB:
lib/Target/Mips/MipsISelDAGToDAG.cpp 256 ISD::SUB, DL, VT, CurDAG->getConstant(0, DL, VT).getNode(), C.getNode());
258 SDValue NewNode = CurDAG->getNode(ISD::SUB, DL, VT, X, NegC);
lib/Target/Mips/MipsISelLowering.cpp 506 setTargetDAGCombine(ISD::SUB);
1176 case ISD::SUB:
lib/Target/Mips/MipsSEISelLowering.cpp 95 setOperationAction(ISD::SUB, VecTys[i], Legal);
343 setOperationAction(ISD::SUB, Ty, Legal);
825 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
2076 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
2266 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2272 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
lib/Target/NVPTX/NVPTXISelLowering.cpp 1996 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2000 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2056 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2060 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4561 return DAG.getNode(ISD::SUB, DL, VT, Num,
lib/Target/PowerPC/PPCFastISel.cpp 1295 case ISD::SUB:
1363 if (ISDOpcode == ISD::SUB)
1965 return SelectBinaryIntOp(I, ISD::SUB);
lib/Target/PowerPC/PPCISelLowering.cpp 564 setOperationAction(ISD::SUB, VT, Legal);
824 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
7070 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
8032 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
8061 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
8089 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
10018 SDValue Y = DAG.getNode(ISD::SUB, dl, VT, Zero, X);
11957 auto SubNode = DAG.getNode(ISD::SUB, DL, MVT::i64, Op0, Op1);
12590 if (LHS.getOpcode() == ISD::SUB && isNullConstant(LHS.getOperand(0)) &&
12596 if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
13833 if (V1.getOpcode() == ISD::SUB &&
13839 if (V2.getOpcode() == ISD::SUB &&
13845 if (V1.getOpcode() == ISD::SUB && V2.getOpcode() == ISD::SUB &&
13845 if (V1.getOpcode() == ISD::SUB && V2.getOpcode() == ISD::SUB &&
14116 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Op);
15382 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Res);
15396 return DAG.getNode(ISD::SUB, DL, VT, Op1, Op0);
15398 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
15481 if (N->getOperand(0).getOpcode() == ISD::SUB) {
15527 if (Cond.getOpcode() != ISD::SETCC || TrueOpnd.getOpcode() != ISD::SUB ||
15528 FalseOpnd.getOpcode() != ISD::SUB)
lib/Target/RISCV/RISCVISelLowering.cpp 104 setOperationAction(ISD::SUB, MVT::i32, Custom);
741 SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt);
791 SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt);
881 case ISD::SUB:
lib/Target/Sparc/SparcISelLowering.cpp 2595 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
lib/Target/SystemZ/SystemZISelLowering.cpp 342 setOperationAction(ISD::SUB, VT, Legal);
2148 if (N->getOpcode() == ISD::SUB &&
2769 return (Neg.getOpcode() == ISD::SUB &&
2783 Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
3243 SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, NeededSpace);
3321 Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
3705 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
3760 NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, DL, MemVT),
3821 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp 257 SDValue Len = DAG.getNode(ISD::SUB, DL, PtrVT, End, Src);
lib/Target/X86/X86FastISel.cpp 2896 BaseOpc = ISD::SUB; CondCode = X86::COND_O; break;
2898 BaseOpc = ISD::SUB; CondCode = X86::COND_B; break;
2918 if (CI->isOne() && (BaseOpc == ISD::ADD || BaseOpc == ISD::SUB) &&
2922 bool IsDec = BaseOpc == ISD::SUB;
lib/Target/X86/X86ISelDAGToDAG.cpp 382 User->getOpcode() == ISD::SUB) {
638 if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB) &&
2010 case ISD::SUB: {
3281 if (ShiftAmt.getOpcode() != ISD::SUB)
3657 if (ShiftAmt->getOpcode() == ISD::ADD || ShiftAmt->getOpcode() == ISD::SUB) {
3667 } else if (ShiftAmt->getOpcode() == ISD::SUB &&
3676 SDValue Neg = CurDAG->getNode(ISD::SUB, DL, SubVT, Zero, Add1);
3842 assert((Node->getOpcode() == ISD::ADD || Node->getOpcode() == ISD::SUB) &&
3873 unsigned NewOpcode = Node->getOpcode() == ISD::ADD ? ISD::SUB : ISD::ADD;
4512 case ISD::SUB: {
4513 if ((Opcode == ISD::ADD || Opcode == ISD::SUB) && NVT.isVector() &&
4560 case ISD::SUB: ROpc = X86::SUB8rr; MOpc = X86::SUB8rm; break;
4570 case ISD::SUB: ROpc = X86::SUB16rr; MOpc = X86::SUB16rm; break;
4580 case ISD::SUB: ROpc = X86::SUB32rr; MOpc = X86::SUB32rm; break;
4590 case ISD::SUB: ROpc = X86::SUB64rr; MOpc = X86::SUB64rm; break;
4601 if (Opcode != ISD::SUB) {
lib/Target/X86/X86ISelLowering.cpp 1026 setOperationAction(ISD::SUB, MVT::i16, Custom);
1027 setOperationAction(ISD::SUB, MVT::i32, Custom);
1189 setOperationAction(ISD::SUB, VT, HasInt256 ? Legal : Custom);
1331 setOperationAction(ISD::SUB, VT, Custom);
1596 setOperationAction(ISD::SUB, VT, Custom);
1858 setTargetDAGCombine(ISD::SUB);
8972 case ISD::SUB: HOpcode = X86ISD::HSUB; break;
9118 else if (isHorizontalBinOpPart(BV, ISD::SUB, DAG, 0, Half, InVec0,
9120 isHorizontalBinOpPart(BV, ISD::SUB, DAG, Half, NumElts, InVec2,
9152 else if (isHorizontalBinOpPart(BV, ISD::SUB, DAG, 0, NumElts, InVec0,
19683 case ISD::SUB: HOpcode = X86ISD::HSUB; break;
20038 case ISD::SUB:
20076 case ISD::SUB:
20093 case ISD::SUB: Opcode = X86ISD::SUB; break;
20358 return DAG.getNode(ISD::SUB, DL, VT, Zero, SRA);
21395 SDValue Mask = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
22225 Result = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
22732 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
22734 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, ParentFrameOffset);
24486 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
24655 return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta);
24931 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, X, Y);
24965 DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Src);
25235 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Fixup);
25601 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
25670 Res = DAG.getNode(ISD::SUB, dl, VT, Res, SignMask);
25792 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
25820 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
25888 SDValue RAmt = DAG.getNode(ISD::SUB, dl, VT, EltBits, Amt);
25907 SDValue RAmt = DAG.getNode(ISD::SUB, dl, VT, EltBits, Amt);
26010 Amt = DAG.getNode(ISD::SUB, dl, ExVT, DAG.getConstant(8, dl, ExVT), Amt);
26393 AmtR = DAG.getNode(ISD::SUB, DL, VT, AmtR, Amt);
27152 RHS = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), RHS);
27765 case ISD::SUB: return lowerAddSub(Op, DAG, Subtarget);
35697 if (AbsOp1.getOpcode() != ISD::SUB)
35949 return DAG.getNode(ISD::SUB, DL, ExtractVT, Zero, Zext);
37117 Other->getOpcode() == ISD::SUB && OpRHS == CondRHS)
37133 OpRHS = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
37786 SDValue Diff = DAG.getNode(ISD::SUB, DL, VT, Const, Add.getOperand(1));
37938 Result = DAG.getNode(isAdd ? ISD::ADD : ISD::SUB, DL, VT, Result,
37948 Result = DAG.getNode(isAdd ? ISD::ADD : ISD::SUB, DL, VT, Result,
38151 NewMul = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
38201 NewMul = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
38220 NewMul = DAG.getNode(ISD::SUB, DL, VT,
38229 NewMul = DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), NewMul);
38231 NewMul = DAG.getNode(ISD::SUB, DL, VT, NewMul, N->getOperand(0));
38244 NewMul = DAG.getNode(ISD::SUB, DL, VT, NewMul, N->getOperand(0));
38245 NewMul = DAG.getNode(ISD::SUB, DL, VT, NewMul, N->getOperand(0));
39023 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, SizeC, Index);
39394 if (!DAG.getTargetLoweringInfo().isOperationLegal(ISD::SUB, MaskVT))
39398 return N->getOpcode() == ISD::SUB && N->getOperand(1) == V &&
39426 SDValue Res = DAG.getNode(ISD::SUB, DL, MaskVT, SubOp1, SubOp2);
39699 if (ShAmt0.getOpcode() == ISD::SUB || ShAmt0.getOpcode() == ISD::XOR) {
39720 if (ShAmt1.getOpcode() == ISD::SUB) {
40144 Operands[1] = DAG.getNode(ISD::SUB, DL, InVT, Operands[1], VecOnes);
41012 case ISD::SUB: {
42474 return DAG.getNode(ISD::SUB, DL, VT, Zext, DAG.getConstant(1, DL, VT));
42827 if (LHS.getOpcode() == ISD::SUB && isNullConstant(LHS.getOperand(0)) &&
42834 if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
43418 case ISD::SUB:
43452 unsigned GenericOpc = X86ISD::ADD == N->getOpcode() ? ISD::ADD : ISD::SUB;
43467 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Op);
43490 if (Op0.getOpcode() == ISD::SUB && isNullConstant(Op1) &&
43536 bool IsSub = N->getOpcode() == ISD::SUB;
44103 return DAG.getNode(ISD::SUB, DL, VT, Op1, SExt);
44111 return DAG.getNode(ISD::SUB, DL, VT, Op0, SExt);
44915 case ISD::SUB: return combineSub(N, DAG, DCI, Subtarget);
45071 case ISD::SUB:
45160 case ISD::SUB: {
lib/Target/X86/X86TargetTransformInfo.cpp 217 { ISD::SUB, MVT::v2i64, 4 },
679 { ISD::SUB, MVT::v32i8, 1 }, // psubb
681 { ISD::SUB, MVT::v16i16, 1 }, // psubw
683 { ISD::SUB, MVT::v8i32, 1 }, // psubd
685 { ISD::SUB, MVT::v4i64, 1 }, // psubq
720 { ISD::SUB, MVT::v32i8, 4 },
722 { ISD::SUB, MVT::v16i16, 4 },
724 { ISD::SUB, MVT::v8i32, 4 },
726 { ISD::SUB, MVT::v4i64, 4 },
861 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/
862 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/
863 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/
lib/Target/XCore/XCoreISelLowering.cpp 96 setOperationAction(ISD::SUB, MVT::i64, Custom);
213 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG);
237 case ISD::SUB:
695 (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
1684 SDValue Result = DAG.getNode(ISD::SUB, dl, VT,
1699 SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);
unittests/CodeGen/AArch64SelectionDAGTest.cpp 191 auto Op = DAG->getNode(ISD::SUB, Loc, IntVT, N0, N1);