|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc113104 /*251871*/ /*SwitchOpcode*/ 76, TARGET_VAL(ISD::SMAX),// ->251950
gen/lib/Target/AArch64/AArch64GenFastISel.inc 7738 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc54999 /*120404*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMAX),
55006 /*120416*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMAX),
55191 /*120836*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMAX),
55260 /*121001*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMAX),
55322 /*121154*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMAX),
55439 /*121359*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMAX),
55489 /*121449*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMAX),
55582 /*121649*/ /*SwitchOpcode*/ 11|128,10/*1291*/, TARGET_VAL(ISD::SMAX),// ->122944
55595 /*121675*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMAX),
55644 /*121786*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMAX),
55684 /*121881*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMAX),
55727 /*121979*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMAX),
55768 /*122076*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMAX),
55838 /*122242*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMAX),
55911 /*122413*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMAX),
55927 /*122441*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMAX),
55955 /*122492*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMAX),
55986 /*122546*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMAX),
56016 /*122599*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMAX),
56067 /*122690*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMAX),
59913 /*131041*/ /*SwitchOpcode*/ 61, TARGET_VAL(ISD::SMAX),// ->131105
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 7708 /* 29403*/ /*SwitchOpcode*/ 104, TARGET_VAL(ISD::SMAX),// ->29510
gen/lib/Target/ARC/ARCGenDAGISel.inc 639 /* 1059*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::SMAX),// ->1110
gen/lib/Target/ARM/ARMGenDAGISel.inc52441 /*116970*/ /*SwitchOpcode*/ 83|128,1/*211*/, TARGET_VAL(ISD::SMAX),// ->117185
gen/lib/Target/ARM/ARMGenFastISel.inc 5178 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/Mips/MipsGenDAGISel.inc28364 /* 53621*/ /*SwitchOpcode*/ 32|128,1/*160*/, TARGET_VAL(ISD::SMAX),// ->53785
gen/lib/Target/Mips/MipsGenFastISel.inc 3421 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc58220 /*123708*/ /*SwitchOpcode*/ 81, TARGET_VAL(ISD::SMAX),// ->123792
gen/lib/Target/PowerPC/PPCGenDAGISel.inc42726 /*107146*/ /*SwitchOpcode*/ 74, TARGET_VAL(ISD::SMAX),// ->107223
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3249 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc78569 /*165156*/ /*SwitchOpcode*/ 117|128,1/*245*/, TARGET_VAL(ISD::SMAX),// ->165405
83643 /*175230*/ /*SwitchOpcode*/ 117|128,1/*245*/, TARGET_VAL(ISD::SMAX),// ->175479
88439 /*184712*/ /*SwitchOpcode*/ 14|128,2/*270*/, TARGET_VAL(ISD::SMAX),// ->184986
94729 /*197250*/ /*SwitchOpcode*/ 10|128,2/*266*/, TARGET_VAL(ISD::SMAX),// ->197520
101386 /*210526*/ /*SwitchOpcode*/ 56|128,2/*312*/, TARGET_VAL(ISD::SMAX),// ->210842
108744 /*225356*/ /*SwitchOpcode*/ 54|128,2/*310*/, TARGET_VAL(ISD::SMAX),// ->225670
115187 /*238410*/ /*SwitchOpcode*/ 52|128,2/*308*/, TARGET_VAL(ISD::SMAX),// ->238722
118927 /*245603*/ /*SwitchOpcode*/ 32|128,1/*160*/, TARGET_VAL(ISD::SMAX),// ->245767
121513 /*250703*/ /*SwitchOpcode*/ 126|128,1/*254*/, TARGET_VAL(ISD::SMAX),// ->250961
124402 /*256196*/ /*SwitchOpcode*/ 47, TARGET_VAL(ISD::SMAX),// ->256246
126829 /*260778*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::SMAX),// ->260829
145600 /*297904*/ OPC_CheckOpcode, TARGET_VAL(ISD::SMAX),
147522 /*301481*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::SMAX),// ->301532
159506 /*324174*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::SMAX),// ->324211
161240 /*327416*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::SMAX),// ->327453
177340 /*359577*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::SMAX),// ->359599
178291 /*361277*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::SMAX),// ->361298
187280 /*378507*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::SMAX),// ->378544
188051 /*379964*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::SMAX),// ->380001
188704 /*381219*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::SMAX),// ->381241
189022 /*381798*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::SMAX),// ->381819
217018 /*441120*/ /*SwitchOpcode*/ 37|128,14/*1829*/, TARGET_VAL(ISD::SMAX),// ->442953
gen/lib/Target/X86/X86GenFastISel.inc13525 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
include/llvm/CodeGen/TargetLowering.h 2263 case ISD::SMAX:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1525 case ISD::SMAX:
4235 case ISD::SMAX: AltOpcode = ISD::UMAX; break;
4237 case ISD::UMAX: AltOpcode = ISD::SMAX; break;
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3089 case ISD::SMAX:
3096 case ISD::SMAX: Pred = ISD::SETGT; break;
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 80 case ISD::SMAX: Res = PromoteIntRes_SExtIntBinOp(N); break;
722 Result = DAG.getNode(ISD::SMAX, dl, PromotedType, Result, SatMin);
1759 case ISD::SMAX:
2081 case ISD::SMAX:
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 436 case ISD::SMAX:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 121 case ISD::SMAX:
955 case ISD::SMAX:
2129 case ISD::VECREDUCE_SMAX: CombineOpc = ISD::SMAX; break;
2745 case ISD::SMAX:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 3271 case ISD::SMAX: {
3274 bool IsMax = (Opcode == ISD::SMAX);
3277 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX))
3603 case ISD::SMAX: {
3606 bool IsMax = (Opcode == ISD::SMAX);
3609 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX))
4709 case ISD::SMAX: return std::make_pair(C1.sge(C2) ? C1 : C2, true);
5108 case ISD::SMAX:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 3290 case SPF_SMAX: Opc = ISD::SMAX; break;
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 265 case ISD::SMAX: return "smax";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 7328 case ISD::VECREDUCE_SMAX: BaseOpcode = ISD::SMAX; break;
lib/CodeGen/TargetLoweringBase.cpp 643 setOperationAction(ISD::SMAX, VT, Expand);
lib/Target/AArch64/AArch64ISelLowering.cpp 877 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
2843 return DAG.getNode(ISD::SMAX, dl, Op.getValueType(),
12083 ReplaceReductionResults(N, Results, DAG, ISD::SMAX, AArch64ISD::SMAXV);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 348 setOperationAction(ISD::SMAX, MVT::i32, Legal);
2640 SDValue B = DAG.getNode(ISD::SMAX, DL, MVT::i32, OneSubExp, Zero);
lib/Target/AMDGPU/SIISelLowering.cpp 436 setOperationAction(ISD::SMAX, MVT::i16, Legal);
606 setOperationAction(ISD::SMAX, MVT::v2i16, Legal);
632 setOperationAction(ISD::SMAX, MVT::v4i16, Custom);
712 setTargetDAGCombine(ISD::SMAX);
4074 case ISD::SMAX:
8995 case ISD::SMAX:
9158 if (Opc == ISD::SMIN && Op0.getOpcode() == ISD::SMAX && Op0.hasOneUse()) {
9290 case ISD::SMAX:
9957 case ISD::SMAX:
lib/Target/ARC/ARCISelLowering.cpp 97 setOperationAction(ISD::SMAX, MVT::i32, Legal);
lib/Target/ARM/ARMISelLowering.cpp 210 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
257 setOperationAction(ISD::SMAX, VT, Legal);
3732 ? ISD::SMIN : ISD::SMAX;
lib/Target/Mips/MipsSEISelLowering.cpp 344 setOperationAction(ISD::SMAX, Ty, Legal);
2009 return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0),
2021 return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0),
lib/Target/NVPTX/NVPTXISelLowering.cpp 497 setOperationAction(ISD::SMAX, Ty, Legal);
lib/Target/PowerPC/PPCISelLowering.cpp 569 setOperationAction(ISD::SMAX, VT, Legal);
575 setOperationAction(ISD::SMAX, VT, Expand);
670 setOperationAction(ISD::SMAX, MVT::v2i64, Expand);
lib/Target/X86/X86ISelLowering.cpp 873 setOperationAction(ISD::SMAX, VT, VT == MVT::v8i16 ? Legal : Custom);
1039 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
1040 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
1205 setOperationAction(ISD::SMAX, MVT::v4i64, Custom);
1221 setOperationAction(ISD::SMAX, VT, HasInt256 ? Legal : Custom);
1450 setOperationAction(ISD::SMAX, VT, Legal);
1544 setOperationAction(ISD::SMAX, VT, Legal);
1678 setOperationAction(ISD::SMAX, VT, Legal);
24999 Opcode = (Opcode == ISD::UMIN ? ISD::SMIN : ISD::SMAX);
25008 case ISD::SMAX: CC = ISD::CondCode::SETGT; break;
27770 case ISD::SMAX:
35758 Extract, BinOp, {ISD::SMAX, ISD::SMIN, ISD::UMAX, ISD::UMIN}, true);
35788 if (BinOp == ISD::SMAX)
39904 if (MatchMinMax(SMin, ISD::SMAX, C1))
39908 if (SDValue SMax = MatchMinMax(In, ISD::SMAX, C1))
39912 return DAG.getNode(ISD::SMAX, DL, InVT, SMin, In.getOperand(1));
39951 if (SDValue SMax = MatchMinMax(SMin, ISD::SMAX, SignedMin))
39954 if (SDValue SMax = MatchMinMax(In, ISD::SMAX, SignedMin))