|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc114637 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::SEXTLOAD) return false;
115444 cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc78823 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::SEXTLOAD) return false;
gen/lib/Target/AMDGPU/R600GenDAGISel.inc12432 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::SEXTLOAD) return false;
gen/lib/Target/ARC/ARCGenDAGISel.inc 1174 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::SEXTLOAD) return false;
gen/lib/Target/ARM/ARMGenDAGISel.inc54499 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::SEXTLOAD) return false;
54810 return cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc72344 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::SEXTLOAD) return false;
gen/lib/Target/Lanai/LanaiGenDAGISel.inc 1402 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::SEXTLOAD) return false;
gen/lib/Target/Mips/MipsGenDAGISel.inc30088 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::SEXTLOAD) return false;
gen/lib/Target/PowerPC/PPCGenDAGISel.inc44349 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::SEXTLOAD) return false;
gen/lib/Target/RISCV/RISCVGenDAGISel.inc13836 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::SEXTLOAD) return false;
gen/lib/Target/Sparc/SparcGenDAGISel.inc 3507 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::SEXTLOAD) return false;
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc30059 return Type == ISD::EXTLOAD || Type == ISD::SEXTLOAD;
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc21277 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::SEXTLOAD) return false;
gen/lib/Target/X86/X86GenDAGISel.inc254210 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::SEXTLOAD) return false;
gen/lib/Target/XCore/XCoreGenDAGISel.inc 2317 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::SEXTLOAD) return false;
include/llvm/CodeGen/BasicTTIImpl.h 724 ((Opcode == Instruction::ZExt) ? ISD::ZEXTLOAD : ISD::SEXTLOAD);
include/llvm/CodeGen/SelectionDAGNodes.h 2612 cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
include/llvm/CodeGen/TargetLowering.h 2391 LType = ISD::SEXTLOAD;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 8748 auto LoadExtOpcode = IsSigned ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
9097 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
9184 Load->getExtensionType() == ISD::SEXTLOAD || Load->isIndexed())
9284 bool isAExtLoad = (ExtLoadType == ISD::SEXTLOAD) ? ISD::isSEXTLoad(N0Node)
9476 ISD::SEXTLOAD, ISD::SIGN_EXTEND))
9480 tryToFoldExtOfMaskedLoad(DAG, TLI, VT, N, N0, ISD::SEXTLOAD,
9491 DAG, *this, TLI, VT, LegalOperations, N, N0, ISD::SEXTLOAD))
9503 if (TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, MemVT) &&
9509 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(LN00), VT,
9817 LN00->getExtensionType() != ISD::SEXTLOAD && LN00->isUnindexed()) {
10182 ExtType = ISD::SEXTLOAD;
10198 if (LN0->getExtensionType() != ISD::SEXTLOAD && MemoryWidth > ShiftAmt)
10246 if (LN0->getExtensionType() == ISD::SEXTLOAD)
10467 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, EVT))) {
10469 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
10483 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, EVT))) {
10485 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
13921 case ISD::SEXTLOAD:
13988 !LDMemType.isVector() && LD->getExtensionType() != ISD::SEXTLOAD) {
15883 TLI.isLoadExtLegal(ISD::SEXTLOAD, LegalizedStoredValTy,
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 757 if (ExtType == ISD::SEXTLOAD)
935 if (ExtType == ISD::SEXTLOAD)
3464 ISD::SEXTLOAD, dl, PTy, Chain, Addr,
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 2673 if (ExtType == ISD::SEXTLOAD) {
2745 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT,
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 731 case ISD::SEXTLOAD:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 334 case ISD::SEXTLOAD:
3894 case ISD::SEXTLOAD: // e.g. i16->i32 = '17' bits known.
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 650 case ISD::SEXTLOAD: OS << ", sext"; break;
682 case ISD::SEXTLOAD: OS << ", sext"; break;
lib/CodeGen/SelectionDAG/TargetLowering.cpp 3173 } else if (LN0->getExtensionType() == ISD::SEXTLOAD) {
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 1170 else if (ExtType == ISD::SEXTLOAD)
1180 if (ExtType == ISD::SEXTLOAD) {
1193 if (ExtType == ISD::SEXTLOAD) {
lib/Target/AArch64/AArch64ISelLowering.cpp 544 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand);
774 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
3287 ExtType = ISD::SEXTLOAD;
11160 ExtType = ISD::SEXTLOAD;
11258 if (ExtType == ISD::SEXTLOAD)
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 425 LoadOp = LdHi->getExtensionType() == ISD::SEXTLOAD ?
453 LoadOp = LdLo->getExtensionType() == ISD::SEXTLOAD ?
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 110 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
118 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
119 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal);
120 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal);
121 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
136 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
139 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
142 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
145 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v3i16, Expand);
148 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
lib/Target/AMDGPU/R600ISelLowering.cpp 75 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
76 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Custom);
77 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Custom);
90 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, MVT::v2i1, Expand);
94 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
1426 if (ExtType == ISD::SEXTLOAD) { // ... ones.
1502 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
1627 Ext = ISD::SEXTLOAD;
lib/Target/AMDGPU/SIISelLowering.cpp 1535 ExtType = ISD::SEXTLOAD;
7237 case ISD::SEXTLOAD:
7294 if (Ld->getExtensionType() == ISD::SEXTLOAD) {
lib/Target/ARM/ARMISelDAGToDAG.cpp 1496 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1500 if (LD->getExtensionType() == ISD::SEXTLOAD) {
1582 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1634 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
lib/Target/ARM/ARMISelLowering.cpp 241 setLoadExtAction(ISD::SEXTLOAD, From, To, Action);
916 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
996 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
13865 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
15272 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
15318 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
lib/Target/AVR/AVRISelLowering.cpp 59 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
lib/Target/BPF/BPFISelLowering.cpp 126 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
128 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
129 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand);
130 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 138 if (ExtType == ISD::SEXTLOAD)
292 IntExt = ISD::SEXTLOAD;
1458 if (L->getExtensionType() != ISD::SEXTLOAD)
lib/Target/Hexagon/HexagonISelLowering.cpp 1392 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
1452 setLoadExtAction(ISD::SEXTLOAD, TargetVT, VT, Expand);
1471 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1474 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
lib/Target/Lanai/LanaiISelLowering.cpp 138 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
lib/Target/MSP430/MSP430ISelLowering.cpp 62 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
64 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
65 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand);
lib/Target/Mips/MipsISelLowering.cpp 318 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
492 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);
2595 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
lib/Target/Mips/MipsSEISelLowering.cpp 77 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand);
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp 899 if (PlainLoad && (PlainLoad->getExtensionType() == ISD::SEXTLOAD))
1038 if (ExtensionType == ISD::SEXTLOAD)
1681 bool IsSigned = LdNode->getExtensionType() == ISD::SEXTLOAD;
lib/Target/NVPTX/NVPTXISelLowering.cpp 469 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
4518 if (ExtType == ISD::SEXTLOAD) {
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 2734 if (InputLoad && InputLoad->getExtensionType() == ISD::SEXTLOAD)
2773 if (InputLoad && InputLoad->getExtensionType() != ISD::SEXTLOAD)
4490 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
4527 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
lib/Target/PowerPC/PPCISelLowering.cpp 165 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
166 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
222 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
664 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
2622 LD->getExtensionType() == ISD::SEXTLOAD &&
7818 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
lib/Target/RISCV/RISCVISelLowering.cpp 80 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD})
lib/Target/Sparc/SparcISelLowering.cpp 1442 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Expand);
1446 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, VT, Expand);
1476 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
lib/Target/SystemZ/SystemZISelLowering.cpp 278 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
312 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
1998 if (Load->getExtensionType() == ISD::SEXTLOAD) {
2031 ISD::SEXTLOAD :
2061 case ISD::SEXTLOAD:
2218 (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 235 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
243 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
250 for (auto Ext : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
lib/Target/X86/X86ISelLowering.cpp 185 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
787 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
1063 for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1238 for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1363 for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1695 for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
44851 ISD::LoadExtType Ext = N->getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
lib/Target/XCore/XCoreISelLowering.cpp 125 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
127 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);