reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc

50476 /*108538*/        OPC_CheckChild2CondCode, ISD::SETOGT,
50504 /*108614*/        OPC_CheckChild2CondCode, ISD::SETOGT,
50978 /*109907*/        OPC_CheckChild2CondCode, ISD::SETOGT,
51006 /*109983*/        OPC_CheckChild2CondCode, ISD::SETOGT,
51480 /*111276*/        OPC_CheckChild2CondCode, ISD::SETOGT,
51508 /*111352*/        OPC_CheckChild2CondCode, ISD::SETOGT,
60969 /*133216*/        OPC_CheckChild2CondCode, ISD::SETOGT,
61426 /*134313*/        OPC_CheckChild2CondCode, ISD::SETOGT,
61890 /*135424*/        OPC_CheckChild2CondCode, ISD::SETOGT,

gen/lib/Target/AMDGPU/R600GenDAGISel.inc

 4299 /* 17635*/            OPC_CheckCondCode, ISD::SETOGT,
 4526 /* 18502*/            OPC_CheckCondCode, ISD::SETOGT,
 4746 /* 19361*/          OPC_CheckCondCode, ISD::SETOGT,
 4890 /* 19985*/          OPC_CheckCondCode, ISD::SETOGT,

gen/lib/Target/Hexagon/HexagonGenDAGISel.inc

30282 /* 58477*/          OPC_CheckChild2CondCode, ISD::SETOGT,
30437 /* 58823*/          OPC_CheckChild2CondCode, ISD::SETOGT,
51942 /* 97902*/          OPC_CheckChild2CondCode, ISD::SETOGT,

gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc

60768 /*128590*/      OPC_CheckChild2CondCode, ISD::SETOGT,
60792 /*128638*/      OPC_CheckChild2CondCode, ISD::SETOGT,
60816 /*128686*/      OPC_CheckChild2CondCode, ISD::SETOGT,
60830 /*128713*/      OPC_CheckChild2CondCode, ISD::SETOGT,
60844 /*128740*/      OPC_CheckChild2CondCode, ISD::SETOGT,
60868 /*128788*/      OPC_CheckChild2CondCode, ISD::SETOGT,
60892 /*128836*/      OPC_CheckChild2CondCode, ISD::SETOGT,
60906 /*128863*/      OPC_CheckChild2CondCode, ISD::SETOGT,
63808 /*134590*/      OPC_CheckChild2CondCode, ISD::SETOGT,
63837 /*134654*/      OPC_CheckChild2CondCode, ISD::SETOGT,
63866 /*134718*/      OPC_CheckChild2CondCode, ISD::SETOGT,
63895 /*134782*/      OPC_CheckChild2CondCode, ISD::SETOGT,
66733 /*141058*/        OPC_CheckChild2CondCode, ISD::SETOGT,
67437 /*142565*/        OPC_CheckChild2CondCode, ISD::SETOGT,
68101 /*143992*/        OPC_CheckChild2CondCode, ISD::SETOGT,

gen/lib/Target/PowerPC/PPCGenDAGISel.inc

25994 /* 62747*/        OPC_CheckChild2CondCode, ISD::SETOGT,
26064 /* 62915*/        OPC_CheckChild2CondCode, ISD::SETOGT,
26350 /* 63731*/        OPC_CheckChild2CondCode, ISD::SETOGT,
26420 /* 63899*/        OPC_CheckChild2CondCode, ISD::SETOGT,
26706 /* 64715*/        OPC_CheckChild2CondCode, ISD::SETOGT,
26894 /* 65227*/        OPC_CheckChild2CondCode, ISD::SETOGT,
27104 /* 65756*/        OPC_CheckChild2CondCode, ISD::SETOGT,

gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc

 7753 /* 14373*/            OPC_CheckChild2CondCode, ISD::SETOGT,
 7829 /* 14512*/            OPC_CheckChild2CondCode, ISD::SETOGT,
 8126 /* 15064*/            OPC_CheckChild2CondCode, ISD::SETOGT,
 8209 /* 15217*/          OPC_CheckChild2CondCode, ISD::SETOGT,

lib/CodeGen/Analysis.cpp

  205   case FCmpInst::FCMP_OGT:   return ISD::SETOGT;
  229     case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT;

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 8158   case ISD::SETOGT:
12297       case ISD::SETOGT:

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 1681     case ISD::SETOGT:

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

  424     case ISD::SETOGT: Result = ISD::SETUGT  ; break;  // SETUGT & SETNE
 1981   case ISD::SETOGT:
 2061     case ISD::SETOGT: return getBoolConstant(R==APFloat::cmpGreaterThan, dl,

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  400     case ISD::SETOGT:                   return "setogt";

lib/CodeGen/SelectionDAG/TargetLowering.cpp

  318   case ISD::SETOGT:
 3736             return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);

lib/Target/AArch64/AArch64ISelLowering.cpp

 1468   case ISD::SETOGT:

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

 1317   case ISD::SETOGT: {
 2049   SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
 2144   SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);

lib/Target/AMDGPU/SIISelLowering.cpp

 7648   SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);

lib/Target/AMDGPU/SIInsertSkips.cpp

  199     case ISD::SETOGT:

lib/Target/ARM/ARMISelLowering.cpp

 1822   case ISD::SETOGT: CondCode = ARMCC::GT; break;
 4619   else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
 6224     case ISD::SETOGT:

lib/Target/Lanai/LanaiISelLowering.cpp

  855   case ISD::SETOGT:

lib/Target/Mips/MipsISelLowering.cpp

  613   case ISD::SETOGT: return Mips::FCOND_OGT;

lib/Target/Mips/MipsSEISelLowering.cpp

  263     setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
  268     setCondCodeAction(ISD::SETOGT, MVT::f64, Expand);
  400     setCondCodeAction(ISD::SETOGT, Ty, Expand);

lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

  544     case ISD::SETOGT:

lib/Target/NVPTX/NVPTXISelLowering.cpp

 2122                    ISD::SETOGT);
 2165                    ISD::SETOGT);

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

 3791         case ISD::SETOGT:
 3818         case ISD::SETOGT:
 3851   case ISD::SETOGT:
 3872   case ISD::SETOGT:
 3909       case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break;
 3918       case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break;
 3932       case ISD::SETOGT:

lib/Target/PowerPC/PPCISelLowering.cpp

 7250     case ISD::SETOGT:

lib/Target/RISCV/RISCVISelLowering.cpp

  144       ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT,

lib/Target/Sparc/SparcISelLowering.cpp

 1392   case ISD::SETOGT: return SPCC::FCC_G;

lib/Target/SystemZ/SystemZISelLowering.cpp

 1945   CONV(GT);
 2615   case ISD::SETOGT:

lib/Target/X86/X86ISelLowering.cpp

 4743   case ISD::SETOGT:
20462   case ISD::SETOGT:
36906       case ISD::SETOGT:
36942       case ISD::SETOGT: