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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc94538 /*214670*/ /*SwitchOpcode*/ 104|128,1/*232*/, TARGET_VAL(ISD::ROTR),// ->214906
94657 /*214912*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
gen/lib/Target/AArch64/AArch64GenFastISel.inc 7735 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc63319 /*138212*/ /*SwitchOpcode*/ 15, TARGET_VAL(ISD::ROTR),// ->138230
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 8590 /* 32958*/ /*SwitchOpcode*/ 104, TARGET_VAL(ISD::ROTR),// ->33065
gen/lib/Target/ARC/ARCGenDAGISel.inc 784 /* 1314*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::ROTR),// ->1365
gen/lib/Target/ARM/ARMGenDAGISel.inc 3401 /* 6922*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
3424 /* 6970*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
3493 /* 7112*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
3516 /* 7160*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
3588 /* 7307*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
3612 /* 7356*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
3684 /* 7501*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
3708 /* 7550*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
4413 /* 8977*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
4434 /* 9019*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
4457 /* 9064*/ OPC_SwitchOpcode /*2 cases */, 1|128,1/*129*/, TARGET_VAL(ISD::ROTR),// ->9198
4598 /* 9356*/ OPC_SwitchOpcode /*2 cases */, 3|128,1/*131*/, TARGET_VAL(ISD::ROTR),// ->9492
8730 /* 18270*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
8752 /* 18316*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
8774 /* 18363*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
8796 /* 18408*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
8818 /* 18454*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
8840 /* 18501*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
13345 /* 28622*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
13402 /* 28745*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
13432 /* 28810*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
13586 /* 29140*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
13643 /* 29262*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
26500 /* 57215*/ /*SwitchOpcode*/ 33, TARGET_VAL(ISD::ROTR),// ->57251
32805 /* 72210*/ /*SwitchOpcode*/ 21|128,2/*277*/, TARGET_VAL(ISD::ROTR),// ->72491
35460 /* 78184*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
gen/lib/Target/ARM/ARMGenFastISel.inc 5174 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
6882 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_imm0_31(VT, RetVT, Op0, Op0IsKill, imm1);
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc63780 /*122292*/ /*SwitchOpcode*/ 74|128,1/*202*/, TARGET_VAL(ISD::ROTR),// ->122498
gen/lib/Target/Mips/MipsGenDAGISel.inc21248 /* 39651*/ /*SwitchOpcode*/ 15|128,1/*143*/, TARGET_VAL(ISD::ROTR),// ->39798
gen/lib/Target/Mips/MipsGenFastISel.inc 3418 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3703 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
3787 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc58664 /*124534*/ /*SwitchOpcode*/ 105, TARGET_VAL(ISD::ROTR),// ->124642
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc12616 /* 24301*/ /*SwitchOpcode*/ 67, TARGET_VAL(ISD::ROTR),// ->24371
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 1914 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc 1888 /* 3867*/ /*SwitchOpcode*/ 44|128,6/*812*/, TARGET_VAL(ISD::ROTR),// ->4683
34062 /* 70843*/ /*SwitchOpcode*/ 97|128,8/*1121*/, TARGET_VAL(ISD::ROTR),// ->71968
79644 /*167242*/ /*SwitchOpcode*/ 80, TARGET_VAL(ISD::ROTR),// ->167325
84634 /*177293*/ /*SwitchOpcode*/ 78, TARGET_VAL(ISD::ROTR),// ->177374
89826 /*187392*/ /*SwitchOpcode*/ 14|128,1/*142*/, TARGET_VAL(ISD::ROTR),// ->187538
95996 /*199888*/ /*SwitchOpcode*/ 10|128,1/*138*/, TARGET_VAL(ISD::ROTR),// ->200030
102903 /*213521*/ /*SwitchOpcode*/ 14|128,1/*142*/, TARGET_VAL(ISD::ROTR),// ->213667
110135 /*228317*/ /*SwitchOpcode*/ 10|128,1/*138*/, TARGET_VAL(ISD::ROTR),// ->228459
116739 /*241343*/ /*SwitchOpcode*/ 6|128,1/*134*/, TARGET_VAL(ISD::ROTR),// ->241481
124784 /*256895*/ /*SwitchOpcode*/ 44, TARGET_VAL(ISD::ROTR),// ->256942
127171 /*261475*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::ROTR),// ->261520
145914 /*298458*/ OPC_CheckOpcode, TARGET_VAL(ISD::ROTR),
147788 /*302015*/ /*SwitchOpcode*/ 20, TARGET_VAL(ISD::ROTR),// ->302038
159810 /*324722*/ /*SwitchOpcode*/ 44, TARGET_VAL(ISD::ROTR),// ->324769
161510 /*327958*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::ROTR),// ->328003
177525 /*359891*/ /*SwitchOpcode*/ 21, TARGET_VAL(ISD::ROTR),// ->359915
178448 /*361577*/ /*SwitchOpcode*/ 20, TARGET_VAL(ISD::ROTR),// ->361600
gen/lib/Target/X86/X86GenFastISel.inc13522 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
14116 case ISD::ROTR: return fastEmit_ISD_ROTR_ri(VT, RetVT, Op0, Op0IsKill, imm1);
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1534 case ISD::ROTR:
5595 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
5596 return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt);
6144 bool HasROTR = hasOperation(ISD::ROTR, VT);
6221 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
6267 LExtOp0, RExtOp0, ISD::ROTL, ISD::ROTR, DL);
6272 RExtOp0, LExtOp0, ISD::ROTR, ISD::ROTL, DL);
7260 if (NextOp == ISD::ROTL || NextOp == ISD::ROTR) {
8000 unsigned RotOpc = IsFSHL ? ISD::ROTL : ISD::ROTR;
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 1175 case ISD::ROTR: {
3327 case ISD::ROTR:
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 1198 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
3620 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 384 case ISD::ROTR:
812 case ISD::ROTR:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 3659 case ISD::ROTR:
3664 if (Opcode == ISD::ROTR)
4707 case ISD::ROTR: return std::make_pair(C1.rotr(C2), true);
5143 case ISD::ROTR:
9158 case ISD::ROTR:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 6245 auto RotateOpcode = IsFSHL ? ISD::ROTL : ISD::ROTR;
6252 RotateOpcode = IsFSHL ? ISD::ROTR : ISD::ROTL;
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 243 case ISD::ROTR: return "rotr";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 2503 case ISD::ROTR: {
5054 if (!isOperationLegalOrCustom(ISD::ROTR, VT))
5059 Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal, Flags);
5273 if (!isOperationLegalOrCustom(ISD::ROTR, VT))
5278 Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal, Flags);
5847 unsigned RevRot = IsLeft ? ISD::ROTR : ISD::ROTL;
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 369 case ISD::ROTR:
2497 case ISD::ROTR:
2921 case ISD::ROTR:
lib/Target/AArch64/AArch64ISelLowering.cpp 312 setOperationAction(ISD::ROTR, VT, Expand);
9892 return DAG.getNode(ISD::ROTR, DL, VT, N0, N1);
9895 return DAG.getNode(ISD::ROTR, DL, VT, N0, N1);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 335 setOperationAction(ISD::ROTR, MVT::i64, Expand);
374 setOperationAction(ISD::ROTR, VT, Expand);
lib/Target/AMDGPU/SIISelLowering.cpp 444 setOperationAction(ISD::ROTR, MVT::i16, Promote);
lib/Target/ARC/ARCISelLowering.cpp 104 setOperationAction(ISD::ROTR, MVT::i32, Legal);
lib/Target/ARM/ARMISelLowering.cpp 1073 setOperationAction(ISD::ROTR, VT, Expand);
13755 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1);
lib/Target/ARM/ARMSelectionDAGInfo.h 29 case ISD::ROTR: return ARM_AM::ror;
lib/Target/AVR/AVRISelLowering.cpp 93 setOperationAction(ISD::ROTR, MVT::i8, Custom);
94 setOperationAction(ISD::ROTR, MVT::i16, Expand);
300 case ISD::ROTR:
319 case ISD::ROTR:
691 case ISD::ROTR:
lib/Target/BPF/BPFISelLowering.cpp 94 setOperationAction(ISD::ROTR, VT, Expand);
lib/Target/Hexagon/HexagonISelLowering.cpp 1375 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR,
1424 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR,
1559 setOperationAction(ISD::ROTR, MVT::i32, Legal);
1560 setOperationAction(ISD::ROTR, MVT::i64, Legal);
lib/Target/Lanai/LanaiISelLowering.cpp 119 setOperationAction(ISD::ROTR, MVT::i32, Expand);
lib/Target/MSP430/MSP430ISelLowering.cpp 78 setOperationAction(ISD::ROTR, MVT::i8, Expand);
80 setOperationAction(ISD::ROTR, MVT::i16, Expand);
lib/Target/Mips/Mips16ISelLowering.cpp 144 setOperationAction(ISD::ROTR, MVT::i32, Expand);
145 setOperationAction(ISD::ROTR, MVT::i64, Expand);
lib/Target/Mips/MipsISelLowering.cpp 431 setOperationAction(ISD::ROTR, MVT::i32, Expand);
434 setOperationAction(ISD::ROTR, MVT::i64, Expand);
lib/Target/NVPTX/NVPTXISelLowering.cpp 424 setOperationAction(ISD::ROTR, MVT::i64, Legal);
426 setOperationAction(ISD::ROTR, MVT::i32, Legal);
429 setOperationAction(ISD::ROTR, MVT::i16, Expand);
431 setOperationAction(ISD::ROTR, MVT::i8, Expand);
lib/Target/PowerPC/PPCISelLowering.cpp 348 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
349 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
660 setOperationAction(ISD::ROTR, VT, Expand);
lib/Target/RISCV/RISCVISelLowering.cpp 137 setOperationAction(ISD::ROTR, XLenVT, Expand);
lib/Target/Sparc/SparcISelLowering.cpp 1571 setOperationAction(ISD::ROTR , MVT::i64, Expand);
1634 setOperationAction(ISD::ROTR , MVT::i32, Expand);
lib/Target/SystemZ/SystemZISelLowering.cpp 195 setOperationAction(ISD::ROTR, VT, Expand);
371 setOperationAction(ISD::ROTR, VT, Expand);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 176 ISD::SREM, ISD::UREM, ISD::ROTL, ISD::ROTR}) {
lib/Target/X86/X86ISelLowering.cpp 771 setOperationAction(ISD::ROTR, VT, Expand);
1460 setOperationAction(ISD::ROTR, VT, Custom);
1553 setOperationAction(ISD::ROTR, VT, Custom);
27750 case ISD::ROTR: return LowerRotate(Op, Subtarget, DAG);
lib/Target/X86/X86TargetTransformInfo.cpp 2291 { ISD::ROTR, MVT::v8i64, 1 },
2292 { ISD::ROTR, MVT::v4i64, 1 },
2293 { ISD::ROTR, MVT::v2i64, 1 },
2294 { ISD::ROTR, MVT::v16i32, 1 },
2295 { ISD::ROTR, MVT::v8i32, 1 },
2296 { ISD::ROTR, MVT::v4i32, 1 }
2308 { ISD::ROTR, MVT::v4i64, 6 },
2309 { ISD::ROTR, MVT::v8i32, 6 },
2310 { ISD::ROTR, MVT::v16i16, 6 },
2311 { ISD::ROTR, MVT::v32i8, 6 },
2312 { ISD::ROTR, MVT::v2i64, 2 },
2313 { ISD::ROTR, MVT::v4i32, 2 },
2314 { ISD::ROTR, MVT::v8i16, 2 },
2315 { ISD::ROTR, MVT::v16i8, 2 }
2319 { ISD::ROTR, MVT::i64, 1 },
2326 { ISD::ROTR, MVT::i32, 1 },
2327 { ISD::ROTR, MVT::i16, 1 },
2328 { ISD::ROTR, MVT::i8, 1 },
2347 ISD = ISD::ROTR;
lib/Target/XCore/XCoreISelLowering.cpp 108 setOperationAction(ISD::ROTR , MVT::i32, Expand);