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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc83080 /*192781*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
88929 /*204467*/ /*SwitchOpcode*/ 79|128,34/*4431*/, TARGET_VAL(ISD::OR),// ->208902
gen/lib/Target/AArch64/AArch64GenFastISel.inc 7734 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc53024 /*115088*/ /*SwitchOpcode*/ 122|128,36/*4730*/, TARGET_VAL(ISD::OR),// ->119822
53516 /*116496*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
53544 /*116555*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
53575 /*116617*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
53603 /*116676*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
53634 /*116738*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
53687 /*116850*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
53748 /*116977*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
53842 /*117289*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
53939 /*117604*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
54033 /*117916*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
54130 /*118231*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
54313 /*118843*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
54522 /*119509*/ /*SwitchOpcode*/ 25, TARGET_VAL(ISD::OR),// ->119537
54565 /*119601*/ /*SwitchOpcode*/ 24, TARGET_VAL(ISD::OR),// ->119628
57592 /*125962*/ /*SwitchOpcode*/ 40, TARGET_VAL(ISD::OR),// ->126005
74343 /*164468*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::OR),// ->164502
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 814 /* 2466*/ /*SwitchOpcode*/ 15|128,116/*14863*/, TARGET_VAL(ISD::OR),// ->17333
1640 /* 5903*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
1736 /* 6323*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
1835 /* 6746*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
1931 /* 7166*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2030 /* 7589*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2198 /* 8341*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2374 /* 9107*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2602 /* 10131*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2833 /* 11158*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
3061 /* 12182*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
3292 /* 13209*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
3734 /* 15219*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
gen/lib/Target/ARC/ARCGenDAGISel.inc 552 /* 906*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::OR),// ->957
gen/lib/Target/ARM/ARMGenDAGISel.inc 57 /* 0*/ OPC_SwitchOpcode /*201 cases */, 118|128,53/*6902*/, TARGET_VAL(ISD::OR),// ->6907
3898 /* 7956*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
3953 /* 8064*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
gen/lib/Target/ARM/ARMGenFastISel.inc 5173 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
6368 case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_mod_imm(VT, RetVT, Op0, Op0IsKill, imm1);
6723 case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_t2_so_imm(VT, RetVT, Op0, Op0IsKill, imm1);
gen/lib/Target/AVR/AVRGenDAGISel.inc 102 /* 81*/ OPC_SwitchOpcode /*2 cases */, 58, TARGET_VAL(ISD::OR),// ->143
875 /* 1476*/ /*SwitchOpcode*/ 62, TARGET_VAL(ISD::OR),// ->1541
gen/lib/Target/BPF/BPFGenDAGISel.inc 1297 /* 2234*/ /*SwitchOpcode*/ 83, TARGET_VAL(ISD::OR),// ->2320
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc 71 /* 32*/ OPC_SwitchOpcode /*2 cases */, 4|128,12/*1540*/, TARGET_VAL(ISD::OR),// ->1577
95 /* 75*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
126 /* 135*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
157 /* 195*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
195 /* 266*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
231 /* 334*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
268 /* 405*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
299 /* 465*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
330 /* 525*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
369 /* 599*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
400 /* 659*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
431 /* 719*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
468 /* 788*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
505 /* 859*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
535 /* 916*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
565 /* 973*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
602 /* 1041*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
637 /* 1106*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
673 /* 1174*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
703 /* 1231*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
733 /* 1288*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
771 /* 1359*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
801 /* 1416*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
831 /* 1473*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
867 /* 1539*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
1967 /* 3654*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
1987 /* 3688*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2012 /* 3736*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2037 /* 3784*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2070 /* 3846*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2095 /* 3894*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2120 /* 3942*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2151 /* 3999*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2177 /* 4047*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2196 /* 4080*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2220 /* 4127*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2244 /* 4174*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2276 /* 4235*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2300 /* 4282*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2324 /* 4329*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2354 /* 4385*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
3058 /* 5735*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
3078 /* 5769*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
3102 /* 5814*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
3126 /* 5859*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
3158 /* 5918*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
3182 /* 5963*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
3206 /* 6008*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
3236 /* 6062*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
3261 /* 6107*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
3280 /* 6140*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
3303 /* 6184*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
3326 /* 6228*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
3357 /* 6286*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
3380 /* 6330*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
3403 /* 6374*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
3432 /* 6427*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4371 /* 8228*/ OPC_SwitchOpcode /*2 cases */, 118|128,13/*1782*/, TARGET_VAL(ISD::OR),// ->10015
4395 /* 8271*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4426 /* 8331*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4457 /* 8391*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4496 /* 8465*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4527 /* 8525*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4558 /* 8585*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4595 /* 8654*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4632 /* 8725*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4663 /* 8785*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4694 /* 8845*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4733 /* 8919*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4764 /* 8979*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4795 /* 9039*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4832 /* 9108*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4869 /* 9179*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4899 /* 9236*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4929 /* 9293*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4967 /* 9364*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4997 /* 9421*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
5027 /* 9478*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
5063 /* 9544*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
5099 /* 9612*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
5129 /* 9669*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
5159 /* 9726*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
5197 /* 9797*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
5227 /* 9854*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
5257 /* 9911*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
5293 /* 9977*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
6565 /* 12426*/ OPC_SwitchOpcode /*2 cases */, 122|128,2/*378*/, TARGET_VAL(ISD::OR),// ->12809
6585 /* 12462*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
6610 /* 12510*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
6635 /* 12558*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
6668 /* 12620*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
6693 /* 12668*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
6718 /* 12716*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
6749 /* 12773*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
7297 /* 13834*/ OPC_SwitchOpcode /*2 cases */, 101|128,2/*357*/, TARGET_VAL(ISD::OR),// ->14196
7317 /* 13870*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
7341 /* 13915*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
7365 /* 13960*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
7397 /* 14019*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
7421 /* 14064*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
7445 /* 14109*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
7475 /* 14163*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
7946 /* 15069*/ OPC_SwitchOpcode /*2 cases */, 127|128,6/*895*/, TARGET_VAL(ISD::OR),// ->15969
7970 /* 15112*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
8001 /* 15172*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
8032 /* 15232*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
8071 /* 15306*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
8102 /* 15366*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
8133 /* 15426*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
8170 /* 15495*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
8207 /* 15566*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
8237 /* 15623*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
8267 /* 15680*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
8305 /* 15751*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
8335 /* 15808*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
8365 /* 15865*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
8401 /* 15931*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
9053 /* 17187*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
9073 /* 17221*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
9098 /* 17269*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
9123 /* 17317*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
9156 /* 17379*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
9181 /* 17427*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
9206 /* 17475*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
9237 /* 17532*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
9263 /* 17580*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
9282 /* 17613*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
9306 /* 17660*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
9330 /* 17707*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
9362 /* 17768*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
9386 /* 17815*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
9410 /* 17862*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
9440 /* 17918*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
10026 /* 19037*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
10046 /* 19071*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
10070 /* 19116*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
10094 /* 19161*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
10126 /* 19220*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
10150 /* 19265*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
10174 /* 19310*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
10204 /* 19364*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
10229 /* 19409*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
10248 /* 19442*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
10271 /* 19486*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
10294 /* 19530*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
10325 /* 19588*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
10348 /* 19632*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
10371 /* 19676*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
10400 /* 19729*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
11331 /* 21515*/ /*SwitchOpcode*/ 60|128,50/*6460*/, TARGET_VAL(ISD::OR),// ->27979
11340 /* 21533*/ OPC_SwitchOpcode /*2 cases */, 127|128,6/*895*/, TARGET_VAL(ISD::OR),// ->22433
11364 /* 21576*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
11395 /* 21636*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
11426 /* 21696*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
11465 /* 21770*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
11496 /* 21830*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
11527 /* 21890*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
11564 /* 21959*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
11601 /* 22030*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
11631 /* 22087*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
11661 /* 22144*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
11699 /* 22215*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
11729 /* 22272*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
11759 /* 22329*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
11795 /* 22395*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
12447 /* 23651*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
12467 /* 23685*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
12492 /* 23733*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
12517 /* 23781*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
12550 /* 23843*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
12575 /* 23891*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
12600 /* 23939*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
12631 /* 23996*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
12657 /* 24044*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
12676 /* 24077*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
12700 /* 24124*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
12724 /* 24171*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
12756 /* 24232*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
12780 /* 24279*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
12804 /* 24326*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
12834 /* 24382*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
13420 /* 25501*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
13440 /* 25535*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
13464 /* 25580*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
13488 /* 25625*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
13520 /* 25684*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
13544 /* 25729*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
13568 /* 25774*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
13598 /* 25828*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
13623 /* 25873*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
13642 /* 25906*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
13665 /* 25950*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
13688 /* 25994*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
13719 /* 26052*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
13742 /* 26096*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
13765 /* 26140*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
13794 /* 26193*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
14970 /* 28448*/ /*SwitchOpcode*/ 45, TARGET_VAL(ISD::OR),// ->28496
15010 /* 28523*/ OPC_SwitchOpcode /*2 cases */, 37|128,3/*421*/, TARGET_VAL(ISD::OR),// ->28949
15995 /* 30579*/ /*SwitchOpcode*/ 82|128,2/*338*/, TARGET_VAL(ISD::OR),// ->30921
16294 /* 31186*/ OPC_SwitchOpcode /*2 cases */, 1|128,1/*129*/, TARGET_VAL(ISD::OR),// ->31320
16467 /* 31521*/ OPC_SwitchOpcode /*2 cases */, 36|128,3/*420*/, TARGET_VAL(ISD::OR),// ->31946
17302 /* 33117*/ /*SwitchOpcode*/ 45, TARGET_VAL(ISD::OR),// ->33165
17342 /* 33192*/ OPC_SwitchOpcode /*2 cases */, 71, TARGET_VAL(ISD::OR),// ->33267
17586 /* 33637*/ /*SwitchOpcode*/ 45, TARGET_VAL(ISD::OR),// ->33685
17626 /* 33712*/ OPC_SwitchOpcode /*2 cases */, 71, TARGET_VAL(ISD::OR),// ->33787
17870 /* 34157*/ /*SwitchOpcode*/ 45, TARGET_VAL(ISD::OR),// ->34205
17910 /* 34232*/ OPC_SwitchOpcode /*2 cases */, 71, TARGET_VAL(ISD::OR),// ->34307
18154 /* 34677*/ /*SwitchOpcode*/ 45, TARGET_VAL(ISD::OR),// ->34725
18194 /* 34752*/ OPC_SwitchOpcode /*2 cases */, 71, TARGET_VAL(ISD::OR),// ->34827
18438 /* 35197*/ /*SwitchOpcode*/ 45, TARGET_VAL(ISD::OR),// ->35245
18478 /* 35272*/ OPC_SwitchOpcode /*2 cases */, 71, TARGET_VAL(ISD::OR),// ->35347
18722 /* 35717*/ /*SwitchOpcode*/ 45, TARGET_VAL(ISD::OR),// ->35765
18762 /* 35792*/ OPC_SwitchOpcode /*2 cases */, 71, TARGET_VAL(ISD::OR),// ->35867
19006 /* 36237*/ /*SwitchOpcode*/ 45, TARGET_VAL(ISD::OR),// ->36285
19046 /* 36312*/ OPC_SwitchOpcode /*2 cases */, 71, TARGET_VAL(ISD::OR),// ->36387
19336 /* 36900*/ /*SwitchOpcode*/ 75, TARGET_VAL(ISD::OR),// ->36978
19388 /* 37020*/ OPC_SwitchOpcode /*2 cases */, 3|128,1/*131*/, TARGET_VAL(ISD::OR),// ->37156
20205 /* 38575*/ /*SwitchOpcode*/ 34|128,69/*8866*/, TARGET_VAL(ISD::OR),// ->47445
20424 /* 38983*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
20583 /* 39273*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
20706 /* 39513*/ /*SwitchOpcode*/ 112|128,5/*752*/, TARGET_VAL(ISD::OR),// ->40269
21125 /* 40287*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
21705 /* 41381*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
21707 /* 41385*/ OPC_SwitchOpcode /*3 cases */, 29|128,4/*541*/, TARGET_VAL(ISD::OR),// ->41931
21971 /* 41957*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
22053 /* 42135*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
22133 /* 42309*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
22214 /* 42483*/ /*SwitchOpcode*/ 22|128,10/*1302*/, TARGET_VAL(ISD::OR),// ->43789
22216 /* 42488*/ OPC_SwitchOpcode /*3 cases */, 3|128,5/*643*/, TARGET_VAL(ISD::OR),// ->43136
22540 /* 43162*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
22642 /* 43374*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
22742 /* 43582*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
22958 /* 44059*/ /*SwitchOpcode*/ 32, TARGET_VAL(ISD::OR),// ->44094
23011 /* 44174*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
23027 /* 44211*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
23103 /* 44367*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::OR),// ->44389
23141 /* 44435*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
23154 /* 44459*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
23250 /* 44654*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::OR),// ->44691
23306 /* 44754*/ /*SwitchOpcode*/ 36, TARGET_VAL(ISD::OR),// ->44793
23403 /* 44951*/ /*SwitchOpcode*/ 56, TARGET_VAL(ISD::OR),// ->45010
23569 /* 45316*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
23585 /* 45353*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
23620 /* 45429*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
23636 /* 45466*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
23671 /* 45542*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
23687 /* 45579*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
23897 /* 46005*/ /*SwitchOpcode*/ 40, TARGET_VAL(ISD::OR),// ->46048
23943 /* 46096*/ /*SwitchOpcode*/ 41, TARGET_VAL(ISD::OR),// ->46140
27309 /* 52587*/ /*SwitchOpcode*/ 32, TARGET_VAL(ISD::OR),// ->52622
27361 /* 52701*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
27377 /* 52739*/ OPC_SwitchOpcode /*2 cases */, 70, TARGET_VAL(ISD::OR),// ->52813
27550 /* 53131*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::OR),// ->53168
27606 /* 53231*/ /*SwitchOpcode*/ 36, TARGET_VAL(ISD::OR),// ->53270
27703 /* 53428*/ /*SwitchOpcode*/ 56, TARGET_VAL(ISD::OR),// ->53487
27869 /* 53793*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
27885 /* 53830*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
27920 /* 53906*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
27936 /* 53943*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
27971 /* 54019*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
27987 /* 54056*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
28197 /* 54482*/ /*SwitchOpcode*/ 40, TARGET_VAL(ISD::OR),// ->54525
28243 /* 54573*/ /*SwitchOpcode*/ 41, TARGET_VAL(ISD::OR),// ->54617
52805 /* 99702*/ OPC_SwitchOpcode /*2 cases */, 92|128,4/*604*/, TARGET_VAL(ISD::OR),// ->100311
54062 /*102153*/ /*SwitchOpcode*/ 16, TARGET_VAL(ISD::OR),// ->102172
54103 /*102229*/ /*SwitchOpcode*/ 17, TARGET_VAL(ISD::OR),// ->102249
57231 /*108688*/ /*SwitchOpcode*/ 101|128,14/*1893*/, TARGET_VAL(ISD::OR),// ->110585
58556 /*111730*/ /*SwitchOpcode*/ 103|128,2/*359*/, TARGET_VAL(ISD::OR),// ->112093
59822 /*114286*/ /*SwitchOpcode*/ 9|128,1/*137*/, TARGET_VAL(ISD::OR),// ->114427
61192 /*116982*/ /*SwitchOpcode*/ 53|128,6/*821*/, TARGET_VAL(ISD::OR),// ->117807
63113 /*120868*/ OPC_SwitchOpcode /*2 cases */, 20|128,2/*276*/, TARGET_VAL(ISD::OR),// ->121149
gen/lib/Target/Lanai/LanaiGenDAGISel.inc 303 /* 468*/ /*SwitchOpcode*/ 124|128,2/*380*/, TARGET_VAL(ISD::OR),// ->852
gen/lib/Target/MSP430/MSP430GenDAGISel.inc 1173 /* 2412*/ /*SwitchOpcode*/ 25|128,3/*409*/, TARGET_VAL(ISD::OR),// ->2825
3758 /* 7592*/ /*SwitchOpcode*/ 72|128,1/*200*/, TARGET_VAL(ISD::OR),// ->7796
gen/lib/Target/Mips/MipsGenDAGISel.inc10854 /* 20297*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
18358 /* 34377*/ /*SwitchOpcode*/ 0|128,17/*2176*/, TARGET_VAL(ISD::OR),// ->36557
gen/lib/Target/Mips/MipsGenFastISel.inc 3417 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc58494 /*124212*/ /*SwitchOpcode*/ 104, TARGET_VAL(ISD::OR),// ->124319
gen/lib/Target/PowerPC/PPCGenDAGISel.inc19525 /* 49381*/ /*SwitchOpcode*/ 46, TARGET_VAL(ISD::OR),// ->49430
20336 /* 51570*/ OPC_SwitchOpcode /*4 cases */, 25, TARGET_VAL(ISD::OR),// ->51599
20431 /* 51722*/ OPC_SwitchOpcode /*2 cases */, 15, TARGET_VAL(ISD::OR),// ->51741
20550 /* 51915*/ OPC_SwitchOpcode /*4 cases */, 25, TARGET_VAL(ISD::OR),// ->51944
20645 /* 52067*/ OPC_SwitchOpcode /*2 cases */, 15, TARGET_VAL(ISD::OR),// ->52086
20723 /* 52196*/ /*SwitchOpcode*/ 30, TARGET_VAL(ISD::OR),// ->52229
23099 /* 56813*/ /*SwitchOpcode*/ 107|128,8/*1131*/, TARGET_VAL(ISD::OR),// ->57948
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3246 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 657 /* 1146*/ OPC_SwitchOpcode /*2 cases */, 57|128,5/*697*/, TARGET_VAL(ISD::OR),// ->1848
2419 /* 4449*/ OPC_SwitchOpcode /*2 cases */, 15|128,1/*143*/, TARGET_VAL(ISD::OR),// ->4597
2751 /* 5076*/ OPC_SwitchOpcode /*2 cases */, 88|128,1/*216*/, TARGET_VAL(ISD::OR),// ->5297
3302 /* 6092*/ OPC_SwitchOpcode /*2 cases */, 120, TARGET_VAL(ISD::OR),// ->6216
3598 /* 6646*/ OPC_SwitchOpcode /*2 cases */, 79, TARGET_VAL(ISD::OR),// ->6729
3776 /* 6976*/ OPC_SwitchOpcode /*2 cases */, 79, TARGET_VAL(ISD::OR),// ->7059
3956 /* 7309*/ OPC_SwitchOpcode /*2 cases */, 6|128,2/*262*/, TARGET_VAL(ISD::OR),// ->7576
4618 /* 8539*/ OPC_SwitchOpcode /*2 cases */, 4|128,2/*260*/, TARGET_VAL(ISD::OR),// ->8804
5264 /* 9749*/ /*SwitchOpcode*/ 1|128,1/*129*/, TARGET_VAL(ISD::OR),// ->9882
gen/lib/Target/Sparc/SparcGenDAGISel.inc 1611 /* 2923*/ /*SwitchOpcode*/ 54|128,1/*182*/, TARGET_VAL(ISD::OR),// ->3109
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc 1798 /* 3412*/ /*SwitchOpcode*/ 64|128,12/*1600*/, TARGET_VAL(ISD::OR),// ->5016
5651 /* 11049*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::OR),// ->11094
6103 /* 11905*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
6205 /* 12088*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
6304 /* 12243*/ /*SwitchOpcode*/ 15, TARGET_VAL(ISD::OR),// ->12261
6404 /* 12399*/ /*SwitchOpcode*/ 15, TARGET_VAL(ISD::OR),// ->12417
6504 /* 12555*/ /*SwitchOpcode*/ 15, TARGET_VAL(ISD::OR),// ->12573
6692 /* 12872*/ /*SwitchOpcode*/ 68|128,75/*9668*/, TARGET_VAL(ISD::OR),// ->22544
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc 136 /* 141*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
170 /* 201*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
272 /* 379*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
306 /* 439*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
408 /* 617*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
442 /* 677*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
544 /* 855*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
578 /* 915*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
680 /* 1093*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
714 /* 1153*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
816 /* 1331*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
850 /* 1391*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
1340 /* 2305*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
1370 /* 2358*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
1884 /* 3330*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
1912 /* 3380*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
1998 /* 3532*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2027 /* 3584*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2114 /* 3738*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2143 /* 3790*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2230 /* 3944*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2259 /* 3996*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2346 /* 4150*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2375 /* 4202*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2462 /* 4356*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2491 /* 4408*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2578 /* 4562*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2607 /* 4614*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2696 /* 4772*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
2726 /* 4826*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
4816 /* 8724*/ /*SwitchOpcode*/ 74, TARGET_VAL(ISD::OR),// ->8801
5016 /* 9111*/ /*SwitchOpcode*/ 46, TARGET_VAL(ISD::OR),// ->9160
5147 /* 9359*/ /*SwitchOpcode*/ 39, TARGET_VAL(ISD::OR),// ->9401
5262 /* 9579*/ /*SwitchOpcode*/ 39, TARGET_VAL(ISD::OR),// ->9621
5377 /* 9799*/ /*SwitchOpcode*/ 39, TARGET_VAL(ISD::OR),// ->9841
5492 /* 10019*/ /*SwitchOpcode*/ 39, TARGET_VAL(ISD::OR),// ->10061
5607 /* 10239*/ /*SwitchOpcode*/ 39, TARGET_VAL(ISD::OR),// ->10281
5722 /* 10459*/ /*SwitchOpcode*/ 39, TARGET_VAL(ISD::OR),// ->10501
5832 /* 10669*/ /*SwitchOpcode*/ 30, TARGET_VAL(ISD::OR),// ->10702
5960 /* 10913*/ /*SwitchOpcode*/ 74, TARGET_VAL(ISD::OR),// ->10990
6169 /* 11318*/ /*SwitchOpcode*/ 64, TARGET_VAL(ISD::OR),// ->11385
6354 /* 11683*/ /*SwitchOpcode*/ 64, TARGET_VAL(ISD::OR),// ->11750
6539 /* 12048*/ /*SwitchOpcode*/ 64, TARGET_VAL(ISD::OR),// ->12115
6724 /* 12413*/ /*SwitchOpcode*/ 64, TARGET_VAL(ISD::OR),// ->12480
6909 /* 12778*/ /*SwitchOpcode*/ 64, TARGET_VAL(ISD::OR),// ->12845
7094 /* 13143*/ /*SwitchOpcode*/ 64, TARGET_VAL(ISD::OR),// ->13210
7275 /* 13500*/ /*SwitchOpcode*/ 56, TARGET_VAL(ISD::OR),// ->13559
8293 /* 15374*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::OR),// ->15408
8351 /* 15488*/ /*SwitchOpcode*/ 33, TARGET_VAL(ISD::OR),// ->15524
8411 /* 15606*/ /*SwitchOpcode*/ 33, TARGET_VAL(ISD::OR),// ->15642
8697 /* 16161*/ /*SwitchOpcode*/ 46|128,1/*174*/, TARGET_VAL(ISD::OR),// ->16339
9344 /* 17466*/ /*SwitchOpcode*/ 122|128,2/*378*/, TARGET_VAL(ISD::OR),// ->17848
10233 /* 19392*/ /*SwitchOpcode*/ 52, TARGET_VAL(ISD::OR),// ->19447
10502 /* 19946*/ /*SwitchOpcode*/ 49|128,2/*305*/, TARGET_VAL(ISD::OR),// ->20255
11206 /* 21476*/ /*SwitchOpcode*/ 52, TARGET_VAL(ISD::OR),// ->21531
11369 /* 21813*/ /*SwitchOpcode*/ 75, TARGET_VAL(ISD::OR),// ->21891
11595 /* 22274*/ /*SwitchOpcode*/ 93, TARGET_VAL(ISD::OR),// ->22370
11831 /* 22766*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::OR),// ->22800
11921 /* 22945*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::OR),// ->22979
12011 /* 23124*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::OR),// ->23158
12101 /* 23303*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::OR),// ->23337
12191 /* 23482*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::OR),// ->23516
12281 /* 23661*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::OR),// ->23695
12371 /* 23840*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::OR),// ->23874
12461 /* 24019*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::OR),// ->24053
12870 /* 24780*/ /*SwitchOpcode*/ 99, TARGET_VAL(ISD::OR),// ->24882
13146 /* 25364*/ /*SwitchOpcode*/ 104, TARGET_VAL(ISD::OR),// ->25471
13426 /* 25969*/ /*SwitchOpcode*/ 104, TARGET_VAL(ISD::OR),// ->26076
13706 /* 26574*/ /*SwitchOpcode*/ 104, TARGET_VAL(ISD::OR),// ->26681
13986 /* 27179*/ /*SwitchOpcode*/ 104, TARGET_VAL(ISD::OR),// ->27286
14266 /* 27784*/ /*SwitchOpcode*/ 104, TARGET_VAL(ISD::OR),// ->27891
14546 /* 28389*/ /*SwitchOpcode*/ 104, TARGET_VAL(ISD::OR),// ->28496
14827 /* 28999*/ /*SwitchOpcode*/ 109, TARGET_VAL(ISD::OR),// ->29111
16842 /* 32652*/ /*SwitchOpcode*/ 103|128,12/*1639*/, TARGET_VAL(ISD::OR),// ->34295
20373 /* 38894*/ /*SwitchOpcode*/ 118, TARGET_VAL(ISD::OR),// ->39015
20674 /* 39505*/ /*SwitchOpcode*/ 62, TARGET_VAL(ISD::OR),// ->39570
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 1912 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc 3803 /* 8151*/ /*SwitchOpcode*/ 103|128,5/*743*/, TARGET_VAL(ISD::OR),// ->8898
9518 /* 20570*/ /*SwitchOpcode*/ 18|128,3/*402*/, TARGET_VAL(ISD::OR),// ->20976
44872 /* 93882*/ /*SwitchOpcode*/ 92|128,43/*5596*/, TARGET_VAL(ISD::OR),// ->99482
76106 /*160432*/ /*SwitchOpcode*/ 76|128,1/*204*/, TARGET_VAL(ISD::OR),// ->160640
79150 /*166313*/ /*SwitchOpcode*/ 29|128,1/*157*/, TARGET_VAL(ISD::OR),// ->166474
80914 /*169713*/ /*SwitchOpcode*/ 70|128,1/*198*/, TARGET_VAL(ISD::OR),// ->169915
84184 /*176383*/ /*SwitchOpcode*/ 25|128,1/*153*/, TARGET_VAL(ISD::OR),// ->176540
86044 /*180149*/ /*SwitchOpcode*/ 118|128,2/*374*/, TARGET_VAL(ISD::OR),// ->180527
89149 /*186082*/ /*SwitchOpcode*/ 14|128,2/*270*/, TARGET_VAL(ISD::OR),// ->186356
91618 /*190946*/ /*SwitchOpcode*/ 106|128,2/*362*/, TARGET_VAL(ISD::OR),// ->191312
95379 /*198600*/ /*SwitchOpcode*/ 10|128,2/*266*/, TARGET_VAL(ISD::OR),// ->198870
98174 /*204361*/ /*SwitchOpcode*/ 118|128,2/*374*/, TARGET_VAL(ISD::OR),// ->204739
102160 /*212064*/ /*SwitchOpcode*/ 14|128,2/*270*/, TARGET_VAL(ISD::OR),// ->212338
104941 /*217600*/ /*SwitchOpcode*/ 106|128,2/*362*/, TARGET_VAL(ISD::OR),// ->217966
109458 /*226882*/ /*SwitchOpcode*/ 10|128,2/*266*/, TARGET_VAL(ISD::OR),// ->227152
112652 /*233523*/ /*SwitchOpcode*/ 16|128,3/*400*/, TARGET_VAL(ISD::OR),// ->233927
116027 /*239970*/ /*SwitchOpcode*/ 52|128,2/*308*/, TARGET_VAL(ISD::OR),// ->240282
123142 /*253955*/ /*SwitchOpcode*/ 124, TARGET_VAL(ISD::OR),// ->254082
124526 /*256433*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::OR),// ->256470
125784 /*258671*/ /*SwitchOpcode*/ 118, TARGET_VAL(ISD::OR),// ->258792
126943 /*261019*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::OR),// ->261056
128623 /*264342*/ /*SwitchOpcode*/ 0|128,5/*640*/, TARGET_VAL(ISD::OR),// ->264986
134228 /*275327*/ /*SwitchOpcode*/ 108|128,4/*620*/, TARGET_VAL(ISD::OR),// ->275951
140540 /*288484*/ /*SwitchOpcode*/ 36|128,1/*164*/, TARGET_VAL(ISD::OR),// ->288652
142512 /*291995*/ /*SwitchOpcode*/ 28|128,1/*156*/, TARGET_VAL(ISD::OR),// ->292155
144504 /*295973*/ /*SwitchOpcode*/ 64, TARGET_VAL(ISD::OR),// ->296040
145722 /*298131*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
146630 /*299696*/ /*SwitchOpcode*/ 61, TARGET_VAL(ISD::OR),// ->299760
147629 /*301706*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::OR),// ->301727
148780 /*303979*/ /*SwitchOpcode*/ 87|128,2/*343*/, TARGET_VAL(ISD::OR),// ->304326
152169 /*310313*/ /*SwitchOpcode*/ 77|128,2/*333*/, TARGET_VAL(ISD::OR),// ->310650
155910 /*317677*/ /*SwitchOpcode*/ 84, TARGET_VAL(ISD::OR),// ->317764
157234 /*319951*/ /*SwitchOpcode*/ 80, TARGET_VAL(ISD::OR),// ->320034
158724 /*322789*/ /*SwitchOpcode*/ 124, TARGET_VAL(ISD::OR),// ->322916
159606 /*324359*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::OR),// ->324396
160548 /*326023*/ /*SwitchOpcode*/ 118, TARGET_VAL(ISD::OR),// ->326144
161330 /*327601*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::OR),// ->327638
162565 /*330048*/ /*SwitchOpcode*/ 0|128,5/*640*/, TARGET_VAL(ISD::OR),// ->330692
167800 /*340311*/ /*SwitchOpcode*/ 108|128,4/*620*/, TARGET_VAL(ISD::OR),// ->340935
173934 /*353114*/ /*SwitchOpcode*/ 36|128,1/*164*/, TARGET_VAL(ISD::OR),// ->353282
175375 /*355708*/ /*SwitchOpcode*/ 28|128,1/*156*/, TARGET_VAL(ISD::OR),// ->355868
176922 /*358867*/ /*SwitchOpcode*/ 64, TARGET_VAL(ISD::OR),// ->358934
177405 /*359687*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::OR),// ->359709
177907 /*360535*/ /*SwitchOpcode*/ 61, TARGET_VAL(ISD::OR),// ->360599
178346 /*361382*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::OR),// ->361403
179347 /*363336*/ /*SwitchOpcode*/ 34|128,5/*674*/, TARGET_VAL(ISD::OR),// ->364014
185121 /*374553*/ /*SwitchOpcode*/ 84, TARGET_VAL(ISD::OR),// ->374640
185890 /*375877*/ /*SwitchOpcode*/ 80, TARGET_VAL(ISD::OR),// ->375960
gen/lib/Target/X86/X86GenFastISel.inc13520 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
14114 case ISD::OR: return fastEmit_ISD_OR_ri(VT, RetVT, Op0, Op0IsKill, imm1);
14245 case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_i64immSExt32(VT, RetVT, Op0, Op0IsKill, imm1);
14350 case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_i16immSExt8(VT, RetVT, Op0, Op0IsKill, imm1);
14454 case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_i32immSExt8(VT, RetVT, Op0, Op0IsKill, imm1);
14558 case ISD::OR: return fastEmit_ISD_OR_ri_Predicate_i64immSExt8(VT, RetVT, Op0, Op0IsKill, imm1);
gen/lib/Target/XCore/XCoreGenDAGISel.inc 2108 /* 3677*/ /*SwitchOpcode*/ 10, TARGET_VAL(ISD::OR),// ->3690
include/llvm/CodeGen/TargetLowering.h 2274 case ISD::OR:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1529 case ISD::OR: return visitOR(N);
1649 case ISD::OR:
1950 (BinOpcode == ISD::AND || BinOpcode == ISD::OR) &&
2148 if (N0.getOpcode() == ISD::OR &&
2308 if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&
2310 return DAG.getNode(ISD::OR, DL, VT, N0, N1);
3741 SDValue IsOneOrAllOnes = DAG.getNode(ISD::OR, DL, CCVT, IsOne, IsAllOnes);
4254 assert((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR ||
4457 SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), OpVT, LL, RL);
4504 SDValue Or = DAG.getNode(ISD::OR, DL, OpVT, XorL, XorR);
4783 if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) &&
4826 case ISD::OR:
5099 if (N0.getOpcode() == ISD::OR &&
5308 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
5529 if (N.getOpcode() == ISD::OR)
5570 } else if (N0.getOpcode() == ISD::OR) {
5597 return DAG.getNode(ISD::OR, DL, VT,
5632 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
5647 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
5662 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0.getOperand(0), N1);
5666 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0.getOperand(1), N1);
5768 return DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N), VT, N0C, N1C);
5772 return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
5797 if (SDValue ROR = reassociateOps(ISD::OR, SDLoc(N), N0, N1, N->getFlags()))
5808 ISD::OR, SDLoc(N1), VT, N1.getNode(), N0.getOperand(1).getNode())) {
5809 SDValue IOR = DAG.getNode(ISD::OR, SDLoc(N0), VT, N0.getOperand(0), N1);
6232 DAG.getNode(ISD::OR, DL, VT, LHSMask, RHSBits));
6237 DAG.getNode(ISD::OR, DL, VT, RHSMask, LHSBits));
6342 case ISD::OR: {
6649 assert(N->getOpcode() == ISD::OR &&
6845 SDValue RHS = DAG.getNode(ISD::OR, DL, VT, M, Y);
6853 return DAG.getNode(ISD::OR, DL, VT, LHS, RHS);
6935 (N0Opcode == ISD::OR || N0Opcode == ISD::AND)) {
6938 unsigned NewOpcode = N0Opcode == ISD::AND ? ISD::OR : ISD::AND;
6947 (N0Opcode == ISD::OR || N0Opcode == ISD::AND)) {
6950 unsigned NewOpcode = N0Opcode == ISD::AND ? ISD::OR : ISD::AND;
7068 if (LogicOpcode != ISD::AND && LogicOpcode != ISD::OR &&
7156 case ISD::OR:
7503 if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR) &&
8203 return DAG.getNode(ISD::OR, DL, VT, Sra, C1);
8338 return DAG.getNode(ISD::OR, DL, VT, N0, N2);
8353 return DAG.getNode(ISD::OR, DL, VT, NOTNode, N1);
8390 if (N0->getOpcode() == ISD::OR && N0->hasOneUse()) {
8430 SDValue Or = DAG.getNode(ISD::OR, DL, N0.getValueType(), N0, N2_0);
9165 if (!(N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
9496 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
9809 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
10495 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
10830 case ISD::OR:
10923 case ISD::OR:
10942 if (N0.getOpcode() == ISD::OR)
11143 return DAG.getNode(ISD::OR, SDLoc(N), VT, X, Cst);
14858 if (Opc == ISD::OR) {
14874 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
16426 if (!Val.getValueType().isScalarInteger() || Val.getOpcode() != ISD::OR)
18150 if (BOpcode != ISD::AND && BOpcode != ISD::OR && BOpcode != ISD::XOR)
lib/CodeGen/SelectionDAG/FastISel.cpp 597 if (VT == MVT::i1 && (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
1831 return selectBinaryOp(I, ISD::OR);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 816 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
847 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1554 SDValue CopiedSign = DAG.getNode(ISD::OR, DL, MagVT, ClearedSign, SignBit);
1679 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1697 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
2565 Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2572 Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2579 Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2595 Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp, Tmp2);
2619 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2620 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2621 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2643 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2644 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2645 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2646 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2647 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2648 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2649 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
3269 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3308 TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3317 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3379 DAG.getNode(ISD::OR, dl, SetCCType, Overflow, Overflow2);
3418 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
4151 Tmp1 = DAG.getNode(ISD::OR, dl, NVT, Tmp1,
4228 case ISD::OR:
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 303 return DAG.getNode(ISD::OR, dl, LVT, LHS, SignBit);
1704 NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3);
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 127 case ISD::OR:
460 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT));
1076 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
1119 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
1344 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
1755 case ISD::OR:
1856 Hi = DAG.getNode(ISD::OR, DL, NVT,
1876 Lo = DAG.getNode(ISD::OR, DL, NVT,
1900 Lo = DAG.getNode(ISD::OR, DL, NVT,
1988 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
2029 HiS = DAG.getNode(ISD::OR, dl, NVT,
2044 LoS = DAG.getNode(ISD::OR, dl, NVT,
2061 LoS = DAG.getNode(ISD::OR, dl, NVT,
2740 ISD::OR, dl, NVT, Lo,
3002 SDValue Tmp = DAG.getNode(ISD::OR, dl, NVT, HLAdjusted, ResultHH);
3038 SatMax = DAG.getNode(ISD::OR, dl, BoolNVT, HHGT0,
3044 SatMin = DAG.getNode(ISD::OR, dl, BoolNVT, HHLT,
3051 SatMax = DAG.getNode(ISD::OR, dl, BoolNVT, HHGT0,
3057 SatMin = DAG.getNode(ISD::OR, dl, BoolNVT, HHLT,
3389 Overflow = DAG.getNode(ISD::OR, dl, BitVT, Overflow, One.getValue(1));
3394 Overflow = DAG.getNode(ISD::OR, dl, BitVT, Overflow, Two.getValue(1));
3409 Overflow = DAG.getNode(ISD::OR, dl, BitVT, Overflow, Five.getValue(1));
3667 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
3952 ISD::OR, dl, NVT, Hi,
lib/CodeGen/SelectionDAG/LegalizeTypes.cpp 974 return DAG.getNode(ISD::OR, dlHi, NVT, Lo, Hi);
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 376 case ISD::OR:
717 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
908 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
938 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
1110 TLI.isOperationLegalOrCustomOrPromote(ISD::OR, ByteVT)))) {
1125 !TLI.isOperationLegalOrCustomOrPromote(ISD::OR, VT))
1152 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
1175 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 134 case ISD::OR:
946 case ISD::OR:
2127 case ISD::VECREDUCE_OR: CombineOpc = ISD::OR; break;
2737 case ISD::OR:
3805 case ISD::OR:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 2154 case ISD::OR:
2697 case ISD::OR:
3577 case ISD::OR:
3969 if ((Op.getOpcode() != ISD::ADD && Op.getOpcode() != ISD::OR) ||
3973 if (Op.getOpcode() == ISD::OR &&
4120 case ISD::OR:
4701 case ISD::OR: return std::make_pair(C1 | C2, true);
5088 case ISD::OR:
5410 case ISD::OR:
lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp 193 case ISD::OR:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 262 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
4867 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
6266 setValue(&I, DAG.getNode(ISD::OR, sdl, VT, ShX, ShY));
6275 SDValue Or = DAG.getNode(ISD::OR, sdl, VT, ShX, ShY);
10078 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h 687 void visitOr (const User &I) { visitBinary(I, ISD::OR); }
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 237 case ISD::OR: return "or";
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 2590 if (N->getOpcode() != ISD::OR) return false;
3623 assert(N->getOpcode() == ISD::OR && "Unexpected opcode");
lib/CodeGen/SelectionDAG/TargetLowering.cpp 402 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
483 case ISD::OR: {
671 case ISD::OR: {
1085 case ISD::OR: {
1172 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, VT, Op0, Op1));
2477 case ISD::OR:
3140 unsigned LogicOpcode = Cond == ISD::SETEQ ? ISD::AND : ISD::OR;
3908 N0 = DAG.getNode(ISD::OR, dl, OpVT, N1, Temp);
3915 N0 = DAG.getNode(ISD::OR, dl, OpVT, N0, Temp);
5711 return DAG.getNode(ISD::OR, dl, VT, Lo, Hi);
5792 !isOperationLegalOrCustomOrPromote(ISD::OR, VT)))
5820 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShX, ShY);
5857 !isOperationLegalOrCustomOrPromote(ISD::OR, VT) ||
5873 Result = DAG.getNode(ISD::OR, DL, VT, DAG.getNode(ShOpc, DL, VT, Op0, And0),
5923 SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
6053 !isOperationLegalOrCustomOrPromote(ISD::OR, SrcVT) ||
6065 SDValue Or = DAG.getNode(ISD::OR, dl, SrcVT, And, Shr);
6090 !isOperationLegalOrCustomOrPromote(ISD::OR, SrcVT) ||
6107 SDValue LoOr = DAG.getNode(ISD::OR, dl, SrcVT, Lo, TwoP52);
6108 SDValue HiOr = DAG.getNode(ISD::OR, dl, SrcVT, Hi, TwoP84);
6250 !isOperationLegalOrCustomOrPromote(ISD::OR, VT)))
6264 Op = DAG.getNode(ISD::OR, dl, VT, Op,
6428 CurrVal = DAG.getNode(ISD::OR, SL, IntVT, CurrVal, ShiftedElt);
6607 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
6936 return DAG.getNode(ISD::OR, dl, VT, SumDiff, OverflowMask);
7326 case ISD::VECREDUCE_OR: BaseOpcode = ISD::OR; break;
lib/CodeGen/TargetLoweringBase.cpp 1608 case Or: return ISD::OR;
lib/Target/AArch64/AArch64FastISel.cpp 1694 static_assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR),
1741 static_assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR),
1964 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 2194 assert(N->getOpcode() == ISD::OR && "Expect a OR operation");
2203 if (!isOpcWithIntImmediate(N, ISD::OR, OrImm))
2283 assert(N->getOpcode() == ISD::OR && "Expect a OR operation");
2442 if (N->getOpcode() != ISD::OR)
2932 case ISD::OR:
lib/Target/AArch64/AArch64ISelLowering.cpp 582 setTargetDAGCombine(ISD::OR);
849 setOperationAction(ISD::OR, VT, Custom);
1036 case ISD::OR:
1764 if (Opcode == ISD::AND || Opcode == ISD::OR) {
1765 bool IsOR = Opcode == ISD::OR;
1853 bool IsOR = Opcode == ISD::OR;
1881 if (Opcode == ISD::OR) {
3053 case ISD::OR:
3927 Bits = DAG.getNode(ISD::OR, DL, Bits.getValueType(), Bits, Arg);
4220 Bits = DAG.getNode(ISD::OR, DL, Bits.getValueType(), Bits, Arg);
5626 DAG.getNode(ISD::OR, dl, VT, LoBitsForLo, HiBitsForLo);
5680 DAG.getNode(ISD::OR, dl, VT, LoBitsForHi, HiBitsForHi);
8198 Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2);
9734 assert(N->getOpcode() == ISD::OR && "Unexpected root");
11737 case ISD::OR:
lib/Target/AArch64/AArch64TargetTransformInfo.cpp 564 case ISD::OR:
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 958 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
2816 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 369 setOperationAction(ISD::OR, VT, Expand);
1563 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));
1824 REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
1829 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
2448 SDValue V = DAG.getNode(ISD::OR, SL, MVT::i32,
2622 MaskedSig = DAG.getNode(ISD::OR, DL, MVT::i32, MaskedSig, U);
2625 M = DAG.getNode(ISD::OR, DL, MVT::i32, M, Lo40Set);
2628 SDValue I = DAG.getNode(ISD::OR, DL, MVT::i32,
2633 SDValue N = DAG.getNode(ISD::OR, DL, MVT::i32, M,
2644 SDValue SigSetHigh = DAG.getNode(ISD::OR, DL, MVT::i32, M,
2650 D = DAG.getNode(ISD::OR, DL, MVT::i32, D, D1);
2661 V1 = DAG.getNode(ISD::OR, DL, MVT::i32, V0, V1);
2675 V = DAG.getNode(ISD::OR, DL, MVT::i32, Sign, V);
lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp 373 case ISD::OR:
lib/Target/AMDGPU/R600ISelLowering.cpp 813 HiSmall = DAG.getNode(ISD::OR, DL, VT, HiSmall, Overflow);
852 LoSmall = DAG.getNode(ISD::OR, DL, VT, LoSmall, Overflow);
1214 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
lib/Target/AMDGPU/SIISelLowering.cpp 551 setOperationAction(ISD::OR, MVT::v2i16, Promote);
552 AddPromotedToType(ISD::OR, MVT::v2i16, MVT::i32);
717 setTargetDAGCombine(ISD::OR);
1379 case ISD::OR:
2539 DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Y) : Y;
2547 DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Z) : Z;
4857 SDValue BFI = DAG.getNode(ISD::OR, SL, IntVT, LHS, RHS);
5005 SDValue Or = DAG.getNode(ISD::OR, SL, MVT::i32, Lo, ShlHi);
8054 if ((N0.getOpcode() != ISD::ADD && N0.getOpcode() != ISD::OR) ||
8086 (N0.getOpcode() == ISD::OR ||
8115 (Opc == ISD::OR && (Val == 0xffffffff || Val == 0)) ||
8155 case ISD::OR:
8206 case ISD::OR:
8519 SDValue LowOr = DAG.getNode(ISD::OR, SL, MVT::i32, LowLHS, ExtSrc);
8533 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::OR, LHS, CRHS))
9997 case ISD::OR:
lib/Target/ARM/ARMFastISel.cpp 1763 case ISD::OR:
2847 return SelectBinaryIntOp(I, ISD::OR);
lib/Target/ARM/ARMISelDAGToDAG.cpp 594 assert(Parent->getOpcode() == ISD::OR && "unexpected parent");
685 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
3173 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
lib/Target/ARM/ARMISelLowering.cpp 194 setOperationAction(ISD::OR, VT, Promote);
195 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
361 setOperationAction(ISD::OR, MVT::v2i64, Legal);
1419 setTargetDAGCombine(ISD::OR);
3644 DAG.getNode(ISD::OR, dl, VTy, SHL, DAG.getConstant(1, dl, VTy));
3664 SDValue ORHi = DAG.getNode(ISD::OR, dl, VTy, SHLHi, Constant1);
4913 return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV);
5486 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
5514 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
5522 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
5810 SDValue LoSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
5850 SDValue HiSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
6241 SDValue Result = DAG.getNode(ISD::OR, dl, CmpVT, TmpOp0, TmpOp1);
6253 SDValue Result = DAG.getNode(ISD::OR, dl, CmpVT, TmpOp0, TmpOp1);
8902 DAG.getNode(ISD::OR, DL, MVT::i32, Lo, Hi));
11599 N1->getOpcode() != ISD::OR && N1->getOpcode() != ISD::XOR)
11672 case ISD::OR:
11691 if (N->getOpcode() != ISD::ADD && N->getOpcode() != ISD::OR &&
13984 if (Op1->getOpcode() != ISD::OR)
14426 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 946 case ISD::OR:
981 if (I->getOpcode() != ISD::OR)
1007 SDValue NewOr = DAG.getNode(ISD::OR, DLS, VT, SX, VOp);
1011 SDValue NewOr = DAG.getNode(ISD::OR, DLS, VT, SY, VOp);
1538 case ISD::OR:
lib/Target/Hexagon/HexagonISelLowering.cpp 1424 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR,
1490 setOperationAction(ISD::OR, NativeVT, Legal);
2192 SDValue B0 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[0], T0});
2193 SDValue B1 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[2], T1});
2512 Rs[i] = DAG.getNode(ISD::OR, dl, MVT::i32, Rs[2*i], Rs[2*i+1]);
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 77 setOperationAction(ISD::OR, T, Legal);
154 setOperationAction(ISD::OR, T, Custom);
180 setOperationAction(ISD::OR, BoolW, Custom);
193 setOperationAction(ISD::OR, BoolV, Legal);
490 SDValue DstV = DAG.getNode(ISD::OR, dl, VecTy, {HalfV0, HalfV1});
1128 Res = DAG.getNode(ISD::OR, dl, ByteTy, Res, Prefixes[e-i-1]);
1539 case ISD::OR:
lib/Target/Lanai/LanaiAluCode.h 130 case ISD::OR:
lib/Target/Lanai/LanaiISelDAGToDAG.cpp 113 if (Addr.getOpcode() == ISD::OR &&
191 if (AluOperator == ISD::OR && RiMode &&
lib/Target/Lanai/LanaiISelLowering.cpp 144 setTargetDAGCombine(ISD::OR);
1140 return DAG.getNode(ISD::OR, DL, MVT::i32,
1153 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1174 return DAG.getNode(ISD::OR, DL, MVT::i32,
1188 return DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1204 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1217 return DAG.getNode(ISD::OR, DL, MVT::i32,
1230 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1266 DAG.getNode(ISD::OR, dl, VT, LoBitsForHi, HiBitsForHi);
1318 DAG.getNode(ISD::OR, dl, MVT::i32, Lo, CarryBits));
1476 case ISD::OR:
lib/Target/MSP430/MSP430ISelDAGToDAG.cpp 222 case ISD::OR:
439 case ISD::OR:
lib/Target/Mips/MipsFastISel.cpp 307 case ISD::OR:
878 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
lib/Target/Mips/MipsISelLowering.cpp 504 setTargetDAGCombine(ISD::OR);
1170 case ISD::OR:
2238 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2296 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2471 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2509 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
4293 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
lib/Target/Mips/MipsSEISelLowering.cpp 164 setTargetDAGCombine(ISD::OR);
337 setOperationAction(ISD::OR, Ty, Legal);
1016 if (NotOp->getOpcode() == ISD::OR)
1033 case ISD::OR:
1694 return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1702 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
2086 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2091 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2097 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
2100 return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
lib/Target/NVPTX/NVPTXISelLowering.cpp 2003 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2063 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2111 DAG.getNode(ISD::OR, SL, MVT::i32, Sign,
lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp 129 case ISD::OR:
lib/Target/PowerPC/PPCFastISel.cpp 1292 case ISD::OR:
1963 return SelectBinaryIntOp(I, ISD::OR);
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 1295 case ISD::OR: {
2517 case ISD::OR:
2526 return Opc == ISD::AND || Opc == ISD::OR || Opc == ISD::XOR;
2702 case ISD::OR: NewOpc = PPC::OR8; break;
3637 case ISD::OR:
3663 case ISD::OR: {
4655 N->getOperand(0).getOpcode() == ISD::OR &&
4683 case ISD::OR: {
5248 assert(N->getOpcode() == ISD::OR &&
5392 if (O.getOpcode() == ISD::OR) {
5536 case ISD::OR:
lib/Target/PowerPC/PPCISelLowering.cpp 609 setOperationAction(ISD::OR , VT, Promote);
610 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
692 setOperationAction(ISD::OR , MVT::v4i32, Legal);
1027 setOperationAction(ISD::OR , MVT::v4i1, Legal);
2299 } else if (N.getOpcode() == ISD::OR) {
2402 } else if (N.getOpcode() == ISD::OR) {
7787 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
8036 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
8040 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
8065 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
8069 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
8093 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
12078 N->getOperand(0).getOpcode() != ISD::OR &&
12090 N->getOperand(1).getOpcode() != ISD::OR &&
12143 BinOp.getOperand(i).getOpcode() == ISD::OR ||
12324 N->getOperand(0).getOpcode() != ISD::OR &&
12356 BinOp.getOperand(i).getOpcode() == ISD::OR ||
lib/Target/RISCV/RISCVISelLowering.cpp 748 SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
797 SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi);
1032 (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR)) {
lib/Target/Sparc/SparcISelLowering.cpp 347 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
1204 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV);
2925 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo);
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 806 case ISD::OR: {
1469 case ISD::OR:
1494 if (ChildOpcode == ISD::AND || ChildOpcode == ISD::OR ||
1498 if (Opcode == ISD::OR && ChildOpcode == ISD::XOR) {
1532 splitLargeImmediate(ISD::OR, Node, SDValue(), Val - uint32_t(Val),
lib/Target/SystemZ/SystemZISelLowering.cpp 268 setOperationAction(ISD::OR, MVT::i64, Custom);
346 setOperationAction(ISD::OR, VT, Legal);
2697 Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GE);
2709 Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GT);
2922 return DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
3718 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
4974 case ISD::OR:
lib/Target/X86/X86ISelDAGToDAG.cpp 599 case ISD::OR:
663 if (U->getOpcode() == ISD::OR || U->getOpcode() == ISD::XOR) {
924 case X86ISD::FOR: Opc = ISD::OR; break;
2080 case ISD::OR:
3425 Control = CurDAG->getNode(ISD::OR, DL, MVT::i32, Control, ShiftAmt);
4303 assert(N->getOpcode() == ISD::OR && "Unexpected opcode!");
4502 case ISD::OR:
4507 if (Opcode == ISD::OR && tryMatchBitSelect(Node))
4562 case ISD::OR: ROpc = X86::OR8rr; MOpc = X86::OR8rm; break;
4572 case ISD::OR: ROpc = X86::OR16rr; MOpc = X86::OR16rm; break;
4582 case ISD::OR: ROpc = X86::OR32rr; MOpc = X86::OR32rm; break;
4592 case ISD::OR: ROpc = X86::OR64rr; MOpc = X86::OR64rm; break;
lib/Target/X86/X86ISelLowering.cpp 1849 setTargetDAGCombine(ISD::OR);
4571 case ISD::OR:
5709 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec);
5756 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec);
5790 Vec = DAG.getNode(ISD::OR, dl, WideOpVT, Low, High);
5791 SubVec = DAG.getNode(ISD::OR, dl, WideOpVT, SubVec, Vec);
6905 case ISD::OR: {
7492 Elt = DAG.getNode(ISD::OR, dl, MVT::i32, NextElt, Elt);
9212 case ISD::OR:
10967 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
11578 DAG.getNode(ISD::OR, DL, MVT::v16i8, LoShift, HiShift));
13940 V = DAG.getNode(ISD::OR, DL, ShufVT, V1, V2);
18626 ISD::OR, dl, MVT::v2i64,
18753 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
18756 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
19962 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
19968 if (!matchScalarReduction(Op, ISD::OR, VecIns))
19989 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
20077 case ISD::OR:
20096 case ISD::OR: Opcode = X86ISD::OR; break;
20891 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
20989 if (Op0.getOpcode() == ISD::OR && Op0.hasOneUse()) {
21016 if (Op0.getOpcode() == ISD::OR && isNullConstant(Op1) &&
21361 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
21372 if ((Op2.getOpcode() == ISD::XOR || Op2.getOpcode() == ISD::OR) &&
21946 if (Opc != ISD::OR && Opc != ISD::AND)
22050 if (CondOpc == ISD::OR) {
23164 SetCC = DAG.getNode(ISD::OR, dl, MVT::i8, SetCC, SetP);
23835 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
24578 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
24909 return DAG.getNode(ISD::OR, dl, VT, X, Y);
26201 ISD::OR, dl, VT,
26355 ISD::OR, DL, VT,
26365 ISD::OR, DL, VT,
26375 ISD::OR, DL, VT,
26396 return DAG.getNode(ISD::OR, DL, VT, SHL, SRL);
26407 return DAG.getNode(ISD::OR, DL, VT, Lo, Hi);
26427 return DAG.getNode(ISD::OR, DL, VT,
26741 return DAG.getNode(ISD::OR, DL, MVT::i64, Lo, Hi);
26750 return DAG.getNode(ISD::OR, DL, MVT::i32, Lo, Hi);
27100 return DAG.getNode(ISD::OR, DL, VT, Lo, Hi);
28231 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
35184 case ISD::OR:
35199 case ISD::OR:
35352 Op.getOpcode() != ISD::OR &&
35661 case ISD::OR: FPOpcode = X86ISD::FOR; break;
35837 SDValue Match = DAG.matchBinOpReduction(Extract, BinOp, {ISD::OR, ISD::AND});
35931 if (BinOp == ISD::OR) {
36603 SDValue Or = DAG.getNode(ISD::OR, DL, CondVT, Cond, CastRHS);
37491 case ISD::OR:
38797 Narrow->getOpcode() != ISD::OR)
38874 case ISD::OR: FPOpcode = X86ISD::FOR; break;
39291 assert(N->getOpcode() == ISD::OR && "Unexpected Opcode");
39333 return DAG.getNode(ISD::OR, DL, VT, X, Y);
39338 if (N->getOpcode() != ISD::OR)
39440 assert(N->getOpcode() == ISD::OR && "Unexpected Opcode");
39518 return (N->getOpcode() == ISD::OR && N->hasOneUse());
39546 OR = (LHS->getOpcode() == ISD::OR) ? LHS.getNode() : RHS.getNode();
39565 Ret = DAG.getNode(ISD::OR, SDLoc(OR), VT, NewLHS, NewRHS);
39576 if (RHS->getOpcode() == ISD::OR)
39581 Ret = DAG.getNode(ISD::OR, SDLoc(OR), VT, Ret, NewRHS);
39609 if (matchScalarReduction(SDValue(N, 0), ISD::OR, SrcOps) &&
40162 if (V.getValueType() != VT || ISD::OR != V.getOpcode() ||
40987 case ISD::OR: {
41704 case X86ISD::FOR: IntOpcode = ISD::OR; break;
42667 bool IsOrXorXorCCZero = isNullConstant(Y) && X.getOpcode() == ISD::OR &&
42765 Cmp = DAG.getNode(ISD::OR, DL, CmpVT, Cmp1, Cmp2);
42769 Cmp = DAG.getNode(ISD::OR, DL, VecVT, Cmp1, Cmp2);
43410 case ISD::OR: NewOpc = X86ISD::OR; break;
44925 case ISD::OR: return combineOr(N, DAG, DCI, Subtarget);
45075 case ISD::OR:
45156 case ISD::OR:
lib/Target/X86/X86TargetTransformInfo.cpp 2641 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp
2642 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp
2650 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp
2651 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp
2652 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp
2653 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp
2661 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp
2662 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp
2663 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp
2664 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp
lib/Target/XCore/XCoreISelLowering.cpp 396 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, LowShifted, HighShifted);
457 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted);