reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenDAGISel.inc

92417 /*210481*/  /*SwitchOpcode*/ 106|128,1/*234*/, TARGET_VAL(ISD::INTRINSIC_VOID),// ->210719

gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc

54661 /*119822*/  /*SwitchOpcode*/ 120|128,2/*376*/, TARGET_VAL(ISD::INTRINSIC_VOID),// ->120202

gen/lib/Target/AMDGPU/R600GenDAGISel.inc

  606 /*  1960*/  /*SwitchOpcode*/ 118|128,3/*502*/, TARGET_VAL(ISD::INTRINSIC_VOID),// ->2466

gen/lib/Target/ARM/ARMGenDAGISel.inc

24276 /* 52414*/  /*SwitchOpcode*/ 13|128,21/*2701*/, TARGET_VAL(ISD::INTRINSIC_VOID),// ->55119

gen/lib/Target/Hexagon/HexagonGenDAGISel.inc

65570 /*126184*/  /*SwitchOpcode*/ 90|128,8/*1114*/, TARGET_VAL(ISD::INTRINSIC_VOID),// ->127302

gen/lib/Target/Mips/MipsGenDAGISel.inc

10709 /* 20063*/  /*SwitchOpcode*/ 95|128,1/*223*/, TARGET_VAL(ISD::INTRINSIC_VOID),// ->20290

gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc

39756 /* 86901*/  /*SwitchOpcode*/ 51|128,83|128,1/*27059*/, TARGET_VAL(ISD::INTRINSIC_VOID),// ->113965

gen/lib/Target/PowerPC/PPCGenDAGISel.inc

 2562 /*  5654*/  /*SwitchOpcode*/ 25|128,8/*1049*/, TARGET_VAL(ISD::INTRINSIC_VOID),// ->6707

gen/lib/Target/SystemZ/SystemZGenDAGISel.inc

15996 /* 29456*/  /*SwitchOpcode*/ 120|128,1/*248*/, TARGET_VAL(ISD::INTRINSIC_VOID),// ->29708

gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc

 9104 /* 17002*/  /*SwitchOpcode*/ 68, TARGET_VAL(ISD::INTRINSIC_VOID),// ->17073

gen/lib/Target/X86/X86GenDAGISel.inc

17832 /* 35972*/  /*SwitchOpcode*/ 111|128,14/*1903*/, TARGET_VAL(ISD::INTRINSIC_VOID),// ->37879

gen/lib/Target/XCore/XCoreGenDAGISel.inc

  621 /*  1011*/  /*SwitchOpcode*/ 87|128,4/*599*/, TARGET_VAL(ISD::INTRINSIC_VOID),// ->1614

include/llvm/CodeGen/SelectionDAGNodes.h

  679             NodeType == ISD::INTRINSIC_VOID) &&

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

  991   case ISD::INTRINSIC_VOID:
 3706   case ISD::INTRINSIC_VOID:

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 3320   case ISD::INTRINSIC_VOID:
 3938       Opcode == ISD::INTRINSIC_VOID) {
 4089         Opcode == ISD::INTRINSIC_VOID) {
 6585   assert((Opcode == ISD::INTRINSIC_VOID ||

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

 2783       DAG.setRoot(DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops));
 4788   if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
 4836     Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  142   case ISD::INTRINSIC_VOID:

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

 3648       N->getOpcode() != ISD::INTRINSIC_VOID) {

lib/CodeGen/SelectionDAG/TargetLowering.cpp

 2585           Op.getOpcode() == ISD::INTRINSIC_VOID) &&
 2620           Op.getOpcode() == ISD::INTRINSIC_VOID) &&
 2632           Op.getOpcode() == ISD::INTRINSIC_VOID) &&
 2644           Op.getOpcode() == ISD::INTRINSIC_VOID) &&
 2658        Op.getOpcode() == ISD::INTRINSIC_VOID) &&
 2692           Op.getOpcode() == ISD::INTRINSIC_VOID) &&

lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

 3360   case ISD::INTRINSIC_VOID: {

lib/Target/AArch64/AArch64ISelLowering.cpp

  615   setTargetDAGCombine(ISD::INTRINSIC_VOID);
 1091   case ISD::INTRINSIC_VOID: {
 8398     Info.opc = ISD::INTRINSIC_VOID;
11776   case ISD::INTRINSIC_VOID:

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

  917   case ISD::INTRINSIC_VOID: {

lib/Target/AMDGPU/R600ISelLowering.cpp

  270   setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
  500   case ISD::INTRINSIC_VOID: {

lib/Target/AMDGPU/SIISelLowering.cpp

  691   setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
  692   setOperationAction(ISD::INTRINSIC_VOID, MVT::v2i16, Custom);
  693   setOperationAction(ISD::INTRINSIC_VOID, MVT::v2f16, Custom);
  694   setOperationAction(ISD::INTRINSIC_VOID, MVT::v4f16, Custom);
  695   setOperationAction(ISD::INTRINSIC_VOID, MVT::v4i16, Custom);
  696   setOperationAction(ISD::INTRINSIC_VOID, MVT::f16, Custom);
  697   setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
  698   setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
  939       Info.opc = ISD::INTRINSIC_VOID;
  979     Info.opc = ISD::INTRINSIC_VOID;
  994     Info.opc = ISD::INTRINSIC_VOID;
 1023     Info.opc = ISD::INTRINSIC_VOID;
 4040   case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
 4467   bool HaveChain = Intr->getOpcode() == ISD::INTRINSIC_VOID ||

lib/Target/ARM/ARMISelDAGToDAG.cpp

 3796   case ISD::INTRINSIC_VOID:

lib/Target/ARM/ARMISelLowering.cpp

  899     setTargetDAGCombine(ISD::INTRINSIC_VOID);
 1051   setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
 3786   return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
 9175   case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG, Subtarget);
12875   const bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
14529   case ISD::INTRINSIC_VOID:
16290     Info.opc = ISD::INTRINSIC_VOID;
16312     Info.opc = ISD::INTRINSIC_VOID;

lib/Target/Hexagon/HexagonISelLowering.cpp

 1303   setOperationAction(ISD::INTRINSIC_VOID,       MVT::Other, Custom);
 2877     case ISD::INTRINSIC_VOID:       return LowerINTRINSIC_VOID(Op, DAG);

lib/Target/Hexagon/HexagonISelLoweringHVX.cpp

 1575     case ISD::INTRINSIC_VOID:          return Op;

lib/Target/Mips/MipsSEISelDAGToDAG.cpp

  866   case ISD::INTRINSIC_VOID: {

lib/Target/Mips/MipsSEISelLowering.cpp

  214   setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
  463   case ISD::INTRINSIC_VOID:     return lowerINTRINSIC_VOID(Op, DAG);

lib/Target/NVPTX/NVPTXISelLowering.cpp

 3684     Info.opc = ISD::INTRINSIC_VOID;
 3705     Info.opc = ISD::INTRINSIC_VOID;
 3726     Info.opc = ISD::INTRINSIC_VOID;
 3743     Info.opc = ISD::INTRINSIC_VOID;

lib/Target/PowerPC/PPCISelLowering.cpp

  475   setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
  476   setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
  477   setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom);
  478   setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
 1126   setTargetDAGCombine(ISD::INTRINSIC_VOID);
 9693   StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
 9892   StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
10174   case ISD::INTRINSIC_VOID:
11816   if (N->getOpcode() == ISD::INTRINSIC_VOID) {
13212   case ISD::INTRINSIC_VOID: {
13868   case ISD::INTRINSIC_VOID:
14759     Info.opc = ISD::INTRINSIC_VOID;
14792     Info.opc = ISD::INTRINSIC_VOID;

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

  266   setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
 1004   case ISD::INTRINSIC_VOID:
 1202   case ISD::INTRINSIC_VOID:

lib/Target/X86/X86ISelDAGToDAG.cpp

 2262       Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
 4362   case ISD::INTRINSIC_VOID: {

lib/Target/X86/X86ISelLowering.cpp

 1772   setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
 4799     Info.opc = ISD::INTRINSIC_VOID;
 4829     Info.opc = ISD::INTRINSIC_VOID;
27726   case ISD::INTRINSIC_VOID:
31492           Opc == ISD::INTRINSIC_VOID) &&

lib/Target/XCore/XCoreISelLowering.cpp

  171   setTargetDAGCombine(ISD::INTRINSIC_VOID);
 1595   case ISD::INTRINSIC_VOID: