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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc94078 /*213830*/ /*SwitchOpcode*/ 49, TARGET_VAL(ISD::FTRUNC),// ->213882
94390 /*214408*/ /*SwitchOpcode*/ 49, TARGET_VAL(ISD::FTRUNC),// ->214460
106056 /*237049*/ /*SwitchOpcode*/ 91, TARGET_VAL(ISD::FTRUNC),// ->237143
gen/lib/Target/AArch64/AArch64GenFastISel.inc 4288 case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc76048 /*168838*/ /*SwitchOpcode*/ 52, TARGET_VAL(ISD::FTRUNC),// ->168893
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 9678 /* 36914*/ /*SwitchOpcode*/ 69, TARGET_VAL(ISD::FTRUNC),// ->36986
gen/lib/Target/ARM/ARMGenDAGISel.inc44946 /* 99439*/ /*SwitchOpcode*/ 112, TARGET_VAL(ISD::FTRUNC),// ->99554
gen/lib/Target/ARM/ARMGenFastISel.inc 2723 case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc71334 /*150422*/ /*SwitchOpcode*/ 61, TARGET_VAL(ISD::FTRUNC),// ->150486
gen/lib/Target/PowerPC/PPCGenDAGISel.inc38817 /* 98137*/ /*SwitchOpcode*/ 113, TARGET_VAL(ISD::FTRUNC),// ->98253
gen/lib/Target/PowerPC/PPCGenFastISel.inc 1710 case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc25056 /* 47469*/ /*SwitchOpcode*/ 33|128,1/*161*/, TARGET_VAL(ISD::FTRUNC),// ->47634
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc19169 /* 36604*/ /*SwitchOpcode*/ 21, TARGET_VAL(ISD::FTRUNC),// ->36628
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 975 case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0, Op0IsKill);
include/llvm/CodeGen/BasicTTIImpl.h 1258 ISDs.push_back(ISD::FTRUNC);
include/llvm/CodeGen/TargetLowering.h 968 case ISD::STRICT_FTRUNC: EqOpc = ISD::FTRUNC; break;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1585 case ISD::FTRUNC: return visitFTRUNC(N);
12805 if (!TLI.isOperationLegal(ISD::FTRUNC, VT) ||
12814 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0.getOperand(0));
12818 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0.getOperand(0));
13128 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0);
13136 case ISD::FTRUNC:
13890 TLI.isOperationLegal(ISD::FTRUNC, STMemType)) {
13891 Val = DAG.getNode(ISD::FTRUNC, SDLoc(ST), STMemType, Val);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3920 case ISD::FTRUNC:
4391 case ISD::FTRUNC:
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 97 case ISD::FTRUNC: R = SoftenFloatRes_FTRUNC(N); break;
1167 case ISD::FTRUNC: ExpandFloatRes_FTRUNC(N, Lo, Hi); break;
2070 case ISD::FTRUNC:
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 423 case ISD::FTRUNC:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 98 case ISD::FTRUNC:
915 case ISD::FTRUNC:
2025 case ISD::FTRUNC:
2867 case ISD::FTRUNC: {
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 4012 case ISD::FTRUNC:
4370 case ISD::FTRUNC: {
4431 case ISD::FTRUNC:
7781 case ISD::STRICT_FTRUNC: NewOpc = ISD::FTRUNC; break;
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 6042 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
7649 if (visitUnaryFloatCall(I, ISD::FTRUNC))
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 199 case ISD::FTRUNC: return "ftrunc";
lib/CodeGen/TargetLoweringBase.cpp 776 setOperationAction(ISD::FTRUNC, VT, Expand);
lib/Target/AArch64/AArch64ISelLowering.cpp 252 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
414 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
442 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
464 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
478 setOperationAction(ISD::FTRUNC, Ty, Legal);
495 setOperationAction(ISD::FTRUNC, MVT::f16, Legal);
681 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
786 setOperationAction(ISD::FTRUNC, Ty, Legal);
796 setOperationAction(ISD::FTRUNC, Ty, Legal);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 257 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
418 setOperationAction(ISD::FTRUNC, VT, Expand);
526 case ISD::FTRUNC:
1140 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
1582 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1684 SDValue Trunc = DAG.getNode(ISD::FTRUNC, DL, MVT::f32, Mul2);
2027 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
2041 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2166 SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X);
2267 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2557 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
3774 case ISD::FTRUNC:
lib/Target/AMDGPU/R600ISelLowering.cpp 153 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
lib/Target/AMDGPU/SIISelLowering.cpp 415 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
420 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
4564 DAG.getNode(ISD::FTRUNC, DL, VT, Op);
8589 case ISD::FTRUNC:
lib/Target/ARM/ARMISelLowering.cpp 791 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
811 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
827 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
956 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
1346 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1362 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
lib/Target/Hexagon/HexagonISelLowering.cpp 1430 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC,
lib/Target/Mips/MipsSEISelLowering.cpp 157 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
lib/Target/NVPTX/NVPTXISelLowering.cpp 549 ISD::FTRUNC}) {
2116 SDValue RoundedA = DAG.getNode(ISD::FTRUNC, SL, VT, AdjustedA);
2128 SDValue RoundedAForSmallA = DAG.getNode(ISD::FTRUNC, SL, VT, A);
2148 SDValue RoundedA = DAG.getNode(ISD::FTRUNC, SL, VT, AdjustedA);
2160 DAG.getNode(ISD::FTRUNC, SL, VT, A);
lib/Target/PowerPC/PPCISelLowering.cpp 238 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
314 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
319 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
643 setOperationAction(ISD::FTRUNC, VT, Expand);
704 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
768 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
899 setOperationAction(ISD::FTRUNC, MVT::f128, Legal);
1052 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1057 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
lib/Target/PowerPC/PPCTargetTransformInfo.cpp 332 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
402 Opcode = ISD::FTRUNC; break;
lib/Target/SystemZ/SystemZISelLowering.cpp 427 setOperationAction(ISD::FTRUNC, VT, Legal);
484 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
516 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 98 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT})
184 for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT,
lib/Target/X86/X86ISelDAGToDAG.cpp 873 case ISD::FTRUNC:
883 case ISD::FTRUNC: Imm = 0xB; break;
5195 case ISD::FTRUNC:
5209 case ISD::FTRUNC: Imm = 0xB; break;
lib/Target/X86/X86ISelLowering.cpp 654 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
758 setOperationAction(ISD::FTRUNC, VT, Expand);
1034 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
1110 setOperationAction(ISD::FTRUNC, VT, Legal);
1425 setOperationAction(ISD::FTRUNC, VT, Legal);
36244 case ISD::FTRUNC: