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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc106107 /*237143*/ /*SwitchOpcode*/ 91, TARGET_VAL(ISD::FSQRT),// ->237237
gen/lib/Target/AArch64/AArch64GenFastISel.inc 4287 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc34506 /* 73182*/ OPC_CheckOpcode, TARGET_VAL(ISD::FSQRT),
75010 /*166162*/ OPC_CheckOpcode, TARGET_VAL(ISD::FSQRT),
76179 /*169151*/ /*SwitchOpcode*/ 50, TARGET_VAL(ISD::FSQRT),// ->169204
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 8913 /* 34094*/ OPC_CheckOpcode, TARGET_VAL(ISD::FSQRT),
9378 /* 35781*/ OPC_CheckOpcode, TARGET_VAL(ISD::FSQRT),
10397 /* 39629*/ /*SwitchOpcode*/ 119|128,3/*503*/, TARGET_VAL(ISD::FSQRT),// ->40136
gen/lib/Target/ARM/ARMGenDAGISel.inc45190 /*100005*/ /*SwitchOpcode*/ 60, TARGET_VAL(ISD::FSQRT),// ->100068
gen/lib/Target/ARM/ARMGenFastISel.inc 2722 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/Mips/MipsGenDAGISel.inc27408 /* 51874*/ /*SwitchOpcode*/ 93, TARGET_VAL(ISD::FSQRT),// ->51970
gen/lib/Target/Mips/MipsGenFastISel.inc 1207 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc70945 /*149590*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FSQRT),// ->149627
gen/lib/Target/PowerPC/PPCGenDAGISel.inc38156 /* 96916*/ /*SwitchOpcode*/ 84, TARGET_VAL(ISD::FSQRT),// ->97003
gen/lib/Target/PowerPC/PPCGenFastISel.inc 1709 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc13594 /* 25449*/ /*SwitchOpcode*/ 95, TARGET_VAL(ISD::FSQRT),// ->25547
gen/lib/Target/Sparc/SparcGenDAGISel.inc 3199 /* 5907*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FSQRT),// ->5944
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc23193 /* 43694*/ /*SwitchOpcode*/ 13|128,1/*141*/, TARGET_VAL(ISD::FSQRT),// ->43839
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc18982 /* 36245*/ /*SwitchOpcode*/ 43, TARGET_VAL(ISD::FSQRT),// ->36291
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 974 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc73344 /*154772*/ /*SwitchOpcode*/ 79|128,6/*847*/, TARGET_VAL(ISD::FSQRT),// ->155623
133490 /*273834*/ /*SwitchOpcode*/ 126, TARGET_VAL(ISD::FSQRT),// ->273963
140033 /*287506*/ /*SwitchOpcode*/ 124, TARGET_VAL(ISD::FSQRT),// ->287633
142249 /*291508*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::FSQRT),// ->291542
144262 /*295493*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::FSQRT),// ->295527
151697 /*309384*/ /*SwitchOpcode*/ 73, TARGET_VAL(ISD::FSQRT),// ->309460
155599 /*317087*/ /*SwitchOpcode*/ 71, TARGET_VAL(ISD::FSQRT),// ->317161
157058 /*319633*/ /*SwitchOpcode*/ 17, TARGET_VAL(ISD::FSQRT),// ->319653
158375 /*322148*/ /*SwitchOpcode*/ 16, TARGET_VAL(ISD::FSQRT),// ->322167
167132 /*338967*/ /*SwitchOpcode*/ 126, TARGET_VAL(ISD::FSQRT),// ->339096
173402 /*352088*/ /*SwitchOpcode*/ 124, TARGET_VAL(ISD::FSQRT),// ->352215
175135 /*355264*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::FSQRT),// ->355298
176599 /*358197*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::FSQRT),// ->358231
184602 /*373551*/ /*SwitchOpcode*/ 125, TARGET_VAL(ISD::FSQRT),// ->373679
185776 /*375669*/ /*SwitchOpcode*/ 17, TARGET_VAL(ISD::FSQRT),// ->375689
186532 /*377122*/ /*SwitchOpcode*/ 16, TARGET_VAL(ISD::FSQRT),// ->377141
233758 /*476682*/ OPC_CheckOpcode, TARGET_VAL(ISD::FSQRT),
234194 /*477596*/ OPC_CheckOpcode, TARGET_VAL(ISD::FSQRT),
237620 /*484846*/ /*SwitchOpcode*/ 49, TARGET_VAL(ISD::FSQRT),// ->484898
240190 /*490212*/ OPC_CheckOpcode, TARGET_VAL(ISD::FSQRT),
240626 /*491126*/ OPC_CheckOpcode, TARGET_VAL(ISD::FSQRT),
244138 /*498555*/ /*SwitchOpcode*/ 49, TARGET_VAL(ISD::FSQRT),// ->498607
gen/lib/Target/X86/X86GenFastISel.inc 5920 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill);
include/llvm/CodeGen/BasicTTIImpl.h 395 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT);
1209 ISDs.push_back(ISD::FSQRT);
include/llvm/CodeGen/TargetLowering.h 946 case ISD::STRICT_FSQRT: EqOpc = ISD::FSQRT; break;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1568 case ISD::FSQRT: return visitFSQRT(N);
12560 if (N1.getOpcode() == ISD::FSQRT) {
12564 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
12572 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
12584 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) {
12587 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) {
12767 if (!DAG.getTargetLoweringInfo().isOperationLegalOrCustom(ISD::FSQRT, VT))
12777 SDValue Sqrt = DAG.getNode(ISD::FSQRT, DL, VT, N->getOperand(0), Flags);
12778 SDValue SqrtSqrt = DAG.getNode(ISD::FSQRT, DL, VT, Sqrt, Flags);
19721 if (NaN->isNaN() && RHS.getOpcode() == ISD::FSQRT) {
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3828 case ISD::FSQRT:
4393 case ISD::FSQRT:
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 95 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break;
1165 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break;
2069 case ISD::FSQRT:
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 412 case ISD::FSQRT:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 97 case ISD::FSQRT:
914 case ISD::FSQRT:
2866 case ISD::FSQRT:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 4047 case ISD::FSQRT: // Need is known positive
7760 case ISD::STRICT_FSQRT: NewOpc = ISD::FSQRT; break;
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 6036 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
7613 if (visitUnaryFloatCall(I, ISD::FSQRT))
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 191 case ISD::FSQRT: return "fsqrt";
lib/Target/AArch64/AArch64FastISel.cpp 3670 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill);
lib/Target/AArch64/AArch64ISelLowering.cpp 250 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
409 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
448 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
462 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
679 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 423 setOperationAction(ISD::FSQRT, VT, Expand);
lib/Target/AMDGPU/SIISelLowering.cpp 7542 if (RHS.getOpcode() == ISD::FSQRT)
8578 case ISD::FSQRT:
8740 case ISD::FSQRT:
lib/Target/ARM/ARMISelLowering.cpp 335 setOperationAction(ISD::FSQRT, VT, Expand);
780 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
801 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
817 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
946 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
lib/Target/Hexagon/HexagonISelLowering.cpp 1383 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
1428 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
lib/Target/Mips/MipsSEISelLowering.cpp 150 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
394 setOperationAction(ISD::FSQRT, Ty, Legal);
1920 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
lib/Target/NVPTX/NVPTXISelLowering.cpp 571 for (const auto &Op : {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS,
lib/Target/PowerPC/PPCISelLowering.cpp 296 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
301 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
632 setOperationAction(ISD::FSQRT, VT, Expand);
722 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
778 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
1069 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1072 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
1075 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
1078 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
1145 setTargetDAGCombine(ISD::FSQRT);
lib/Target/PowerPC/PPCTargetTransformInfo.cpp 329 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
378 Opcode = ISD::FSQRT; break;
lib/Target/Sparc/SparcISelLowering.cpp 1715 setOperationAction(ISD::FSQRT, MVT::f128, Legal);
1740 setOperationAction(ISD::FSQRT, MVT::f128, Custom);
1792 setOperationAction(ISD::FSQRT, MVT::f32, Promote);
3046 case ISD::FSQRT: return LowerF128Op(Op, DAG,
lib/Target/SystemZ/SystemZISelLowering.cpp 479 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
511 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 194 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
lib/Target/X86/X86ISelLowering.cpp 684 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
36241 case ISD::FSQRT:
lib/Target/X86/X86IntrinsicsInfo.h 919 X86_INTRINSIC_DATA(avx512_sqrt_pd_512, INTR_TYPE_1OP, ISD::FSQRT, X86ISD::FSQRT_RND),
920 X86_INTRINSIC_DATA(avx512_sqrt_ps_512, INTR_TYPE_1OP, ISD::FSQRT, X86ISD::FSQRT_RND),
lib/Target/X86/X86TargetTransformInfo.cpp 1988 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/
1989 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/
1990 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/
1991 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/
1992 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/
1993 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/
2025 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/
2026 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/
2027 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/
2028 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/
2029 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/
2030 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/
2033 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss
2034 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps
2035 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd
2036 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd
2039 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss
2040 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps
2041 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd
2042 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd
2047 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/
2048 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/
2099 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/
2100 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/
2103 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/
2104 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/
2180 ISD = ISD::FSQRT;