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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc106005 /*236955*/ /*SwitchOpcode*/ 91, TARGET_VAL(ISD::FRINT),// ->237049
gen/lib/Target/AArch64/AArch64GenFastISel.inc 4285 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc76094 /*168948*/ /*SwitchOpcode*/ 52, TARGET_VAL(ISD::FRINT),// ->169003
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 9718 /* 37058*/ /*SwitchOpcode*/ 69, TARGET_VAL(ISD::FRINT),// ->37130
gen/lib/Target/ARM/ARMGenDAGISel.inc45020 /* 99617*/ /*SwitchOpcode*/ 112, TARGET_VAL(ISD::FRINT),// ->99732
gen/lib/Target/ARM/ARMGenFastISel.inc 2720 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/Mips/MipsGenDAGISel.inc29736 /* 56616*/ /*SwitchOpcode*/ 25, TARGET_VAL(ISD::FRINT),// ->56644
gen/lib/Target/Mips/MipsGenFastISel.inc 1206 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc71396 /*150550*/ /*SwitchOpcode*/ 61, TARGET_VAL(ISD::FRINT),// ->150614
gen/lib/Target/PowerPC/PPCGenDAGISel.inc38987 /* 98473*/ /*SwitchOpcode*/ 20, TARGET_VAL(ISD::FRINT),// ->98496
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc24434 /* 46107*/ /*SwitchOpcode*/ 15|128,1/*143*/, TARGET_VAL(ISD::FRINT),// ->46254
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc19195 /* 36652*/ /*SwitchOpcode*/ 21, TARGET_VAL(ISD::FRINT),// ->36676
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 973 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill);
include/llvm/CodeGen/BasicTTIImpl.h 1264 ISDs.push_back(ISD::FRINT);
include/llvm/CodeGen/TargetLowering.h 959 case ISD::STRICT_FRINT: EqOpc = ISD::FRINT; break;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp13135 case ISD::FRINT:
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3938 case ISD::FRINT:
4388 case ISD::FRINT:
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 92 case ISD::FRINT: R = SoftenFloatRes_FRINT(N); break;
1162 case ISD::FRINT: ExpandFloatRes_FRINT(N, Lo, Hi); break;
2066 case ISD::FRINT:
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 424 case ISD::FRINT:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 94 case ISD::FRINT:
911 case ISD::FRINT:
2863 case ISD::FRINT:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 4016 case ISD::FRINT:
7772 case ISD::STRICT_FRINT: NewOpc = ISD::FRINT; break;
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 6043 case Intrinsic::rint: Opcode = ISD::FRINT; break;
7637 if (visitUnaryFloatCall(I, ISD::FRINT))
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 205 case ISD::FRINT: return "frint";
lib/CodeGen/TargetLoweringBase.cpp 775 setOperationAction(ISD::FRINT, VT, Expand);
lib/Target/AArch64/AArch64ISelLowering.cpp 247 setOperationAction(ISD::FRINT, MVT::f128, Expand);
412 setOperationAction(ISD::FRINT, MVT::f16, Promote);
446 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
461 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
477 setOperationAction(ISD::FRINT, Ty, Legal);
494 setOperationAction(ISD::FRINT, MVT::f16, Legal);
676 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
785 setOperationAction(ISD::FRINT, Ty, Legal);
795 setOperationAction(ISD::FRINT, Ty, Legal);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 256 setOperationAction(ISD::FRINT, MVT::f32, Legal);
421 setOperationAction(ISD::FRINT, VT, Expand);
527 case ISD::FRINT:
1141 case ISD::FRINT: return LowerFRINT(Op, DAG);
2153 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
3775 case ISD::FRINT:
lib/Target/AMDGPU/R600ISelLowering.cpp 154 setOperationAction(ISD::FRINT, MVT::f64, Custom);
lib/Target/AMDGPU/SIISelLowering.cpp 417 setOperationAction(ISD::FRINT, MVT::f64, Legal);
421 setOperationAction(ISD::FRINT, MVT::f64, Custom);
8590 case ISD::FRINT:
lib/Target/ARM/ARMISelLowering.cpp 792 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
812 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
828 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
957 setOperationAction(ISD::FRINT, MVT::f64, Expand);
1348 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1364 setOperationAction(ISD::FRINT, MVT::f64, Legal);
lib/Target/Hexagon/HexagonISelLowering.cpp 1431 ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR,
lib/Target/Mips/MipsSEISelLowering.cpp 147 setOperationAction(ISD::FRINT, MVT::f16, Promote);
393 setOperationAction(ISD::FRINT, Ty, Legal);
1917 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
lib/Target/NVPTX/NVPTXISelLowering.cpp 548 for (const auto &Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FRINT,
lib/Target/PowerPC/PPCISelLowering.cpp 239 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
644 setOperationAction(ISD::FRINT, VT, Expand);
900 setOperationAction(ISD::FRINT, MVT::f128, Legal);
1064 setOperationAction(ISD::FRINT, MVT::v4f64, Expand);
1065 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
lib/Target/PowerPC/PPCTargetTransformInfo.cpp 333 case Intrinsic::rint: Opcode = ISD::FRINT; break;
394 Opcode = ISD::FRINT; break;
lib/Target/SystemZ/SystemZISelLowering.cpp 420 setOperationAction(ISD::FRINT, VT, Legal);
480 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
512 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 98 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT})
186 ISD::FEXP, ISD::FEXP2, ISD::FRINT}) {
lib/Target/X86/X86ISelDAGToDAG.cpp 875 case ISD::FRINT: {
885 case ISD::FRINT: Imm = 0x4; break;
5197 case ISD::FRINT: {
5211 case ISD::FRINT: Imm = 0x4; break;
lib/Target/X86/X86ISelLowering.cpp 655 setOperationAction(ISD::FRINT, MVT::f80, Expand);
759 setOperationAction(ISD::FRINT, VT, Expand);
1035 setOperationAction(ISD::FRINT, RoundedTy, Legal);
1111 setOperationAction(ISD::FRINT, VT, Legal);
1426 setOperationAction(ISD::FRINT, VT, Legal);
36242 case ISD::FRINT: