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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc101993 /*228399*/ /*SwitchOpcode*/ 23|128,27/*3479*/, TARGET_VAL(ISD::FMA),// ->231882
105421 /*235876*/ /*SwitchOpcode*/ 45, TARGET_VAL(ISD::FMA),// ->235924
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc73317 /*161895*/ /*SwitchOpcode*/ 87|128,1/*215*/, TARGET_VAL(ISD::FMA),// ->162114
73416 /*162175*/ /*SwitchOpcode*/ 50, TARGET_VAL(ISD::FMA),// ->162228
74728 /*165389*/ /*SwitchOpcode*/ 105, TARGET_VAL(ISD::FMA),// ->165497
74739 /*165406*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMA),
77217 /*171676*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::FMA),// ->171727
77261 /*171783*/ /*SwitchOpcode*/ 47, TARGET_VAL(ISD::FMA),// ->171833
gen/lib/Target/AMDGPU/R600GenDAGISel.inc10351 /* 39449*/ /*SwitchOpcode*/ 103, TARGET_VAL(ISD::FMA),// ->39555
gen/lib/Target/ARM/ARMGenDAGISel.inc43545 /* 96081*/ /*SwitchOpcode*/ 94|128,3/*478*/, TARGET_VAL(ISD::FMA),// ->96563
43757 /* 96571*/ OPC_SwitchOpcode /*3 cases */, 33|128,1/*161*/, TARGET_VAL(ISD::FMA),// ->96737
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc68275 /*132199*/ /*SwitchOpcode*/ 59, TARGET_VAL(ISD::FMA),// ->132261
gen/lib/Target/Mips/MipsGenDAGISel.inc29702 /* 56548*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::FMA),// ->56582
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc69520 /*146899*/ /*SwitchOpcode*/ 48|128,2/*304*/, TARGET_VAL(ISD::FMA),// ->147207
gen/lib/Target/PowerPC/PPCGenDAGISel.inc35960 /* 92442*/ /*SwitchOpcode*/ 97, TARGET_VAL(ISD::FMA),// ->92542
36045 /* 92601*/ OPC_SwitchOpcode /*2 cases */, 71, TARGET_VAL(ISD::FMA),// ->92676
36150 /* 92786*/ OPC_SwitchOpcode /*2 cases */, 71, TARGET_VAL(ISD::FMA),// ->92861
36223 /* 92919*/ OPC_SwitchOpcode /*2 cases */, 86, TARGET_VAL(ISD::FMA),// ->93009
37404 /* 95536*/ /*SwitchOpcode*/ 106|128,5/*746*/, TARGET_VAL(ISD::FMA),// ->96286
gen/lib/Target/RISCV/RISCVGenDAGISel.inc12918 /* 24077*/ /*SwitchOpcode*/ 92|128,3/*476*/, TARGET_VAL(ISD::FMA),// ->24557
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc22315 /* 41946*/ /*SwitchOpcode*/ 59|128,2/*315*/, TARGET_VAL(ISD::FMA),// ->42265
23916 /* 45076*/ /*SwitchOpcode*/ 97, TARGET_VAL(ISD::FMA),// ->45176
24099 /* 45405*/ /*SwitchOpcode*/ 71, TARGET_VAL(ISD::FMA),// ->45479
gen/lib/Target/X86/X86GenDAGISel.inc35622 /* 74186*/ OPC_SwitchOpcode /*4 cases */, 89|128,3/*473*/, TARGET_VAL(ISD::FMA),// ->74664
65171 /*137781*/ /*SwitchOpcode*/ 95|128,20/*2655*/, TARGET_VAL(ISD::FMA),// ->140440
131494 /*269903*/ /*SwitchOpcode*/ 49|128,3/*433*/, TARGET_VAL(ISD::FMA),// ->270340
137015 /*281133*/ /*SwitchOpcode*/ 75|128,6/*843*/, TARGET_VAL(ISD::FMA),// ->281980
141837 /*290776*/ /*SwitchOpcode*/ 37, TARGET_VAL(ISD::FMA),// ->290816
143708 /*294365*/ /*SwitchOpcode*/ 105, TARGET_VAL(ISD::FMA),// ->294473
150506 /*307190*/ /*SwitchOpcode*/ 124|128,1/*252*/, TARGET_VAL(ISD::FMA),// ->307446
153776 /*313500*/ /*SwitchOpcode*/ 103|128,3/*487*/, TARGET_VAL(ISD::FMA),// ->313991
156802 /*319201*/ /*SwitchOpcode*/ 21, TARGET_VAL(ISD::FMA),// ->319225
158063 /*321538*/ /*SwitchOpcode*/ 53, TARGET_VAL(ISD::FMA),// ->321594
165262 /*335264*/ /*SwitchOpcode*/ 49|128,3/*433*/, TARGET_VAL(ISD::FMA),// ->335701
170498 /*345937*/ /*SwitchOpcode*/ 75|128,6/*843*/, TARGET_VAL(ISD::FMA),// ->346784
174820 /*354694*/ /*SwitchOpcode*/ 37, TARGET_VAL(ISD::FMA),// ->354734
176126 /*357223*/ /*SwitchOpcode*/ 105, TARGET_VAL(ISD::FMA),// ->357331
181925 /*368391*/ /*SwitchOpcode*/ 97|128,5/*737*/, TARGET_VAL(ISD::FMA),// ->369132
185592 /*375357*/ /*SwitchOpcode*/ 21, TARGET_VAL(ISD::FMA),// ->375381
186280 /*376626*/ /*SwitchOpcode*/ 53, TARGET_VAL(ISD::FMA),// ->376682
232106 /*473325*/ OPC_SwitchOpcode /*8 cases */, 47|128,5/*687*/, TARGET_VAL(ISD::FMA),// ->474017
234220 /*477647*/ OPC_SwitchOpcode /*8 cases */, 56|128,1/*184*/, TARGET_VAL(ISD::FMA),// ->477836
235210 /*479744*/ /*SwitchOpcode*/ 127|128,4/*639*/, TARGET_VAL(ISD::FMA),// ->480387
236897 /*483288*/ /*SwitchOpcode*/ 50|128,1/*178*/, TARGET_VAL(ISD::FMA),// ->483470
237881 /*485412*/ /*SwitchOpcode*/ 29|128,2/*285*/, TARGET_VAL(ISD::FMA),// ->485701
238538 /*486855*/ OPC_SwitchOpcode /*8 cases */, 47|128,5/*687*/, TARGET_VAL(ISD::FMA),// ->487547
240652 /*491177*/ OPC_SwitchOpcode /*8 cases */, 56|128,1/*184*/, TARGET_VAL(ISD::FMA),// ->491366
241642 /*493274*/ /*SwitchOpcode*/ 127|128,4/*639*/, TARGET_VAL(ISD::FMA),// ->493917
243414 /*496995*/ /*SwitchOpcode*/ 50|128,1/*178*/, TARGET_VAL(ISD::FMA),// ->497177
244399 /*499121*/ /*SwitchOpcode*/ 29|128,2/*285*/, TARGET_VAL(ISD::FMA),// ->499410
include/llvm/CodeGen/BasicTTIImpl.h 1273 ISDs.push_back(ISD::FMA);
1276 ISDs.push_back(ISD::FMA);
include/llvm/CodeGen/TargetLowering.h 949 case ISD::STRICT_FMA: EqOpc = ISD::FMA; break;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1565 case ISD::FMA: return visitFMA(N);
11338 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT));
11357 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA;
11549 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT));
11569 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA;
11847 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT));
11859 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA;
12342 return DAG.getNode(ISD::FMA, DL, VT, N0, N1, N2);
12351 return DAG.getNode(ISD::FMA, DL, VT, NegN0, NegN1, N2, Flags);
12369 return DAG.getNode(ISD::FMA, SDLoc(N), VT, N1, N0, N2);
12385 return DAG.getNode(ISD::FMA, DL, VT,
12413 return DAG.getNode(ISD::FMA, DL, VT, N0.getOperand(0),
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 4018 case ISD::FMA:
4361 case ISD::FMA:
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 82 case ISD::FMA: R = SoftenFloatRes_FMA(N); break;
1155 case ISD::FMA: ExpandFloatRes_FMA(N, Lo, Hi); break;
2085 case ISD::FMA: // FMA is same as FMAD
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 430 case ISD::FMA:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 146 case ISD::FMA:
964 case ISD::FMA:
2897 case ISD::FMA:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 4039 case ISD::FMA:
5450 case ISD::FMA: {
7759 case ISD::STRICT_FMA: NewOpc = ISD::FMA; break;
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 6103 setValue(&I, DAG.getNode(ISD::FMA, sdl,
6147 setValue(&I, DAG.getNode(ISD::FMA, sdl,
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 254 case ISD::FMA: return "fma";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 5427 case ISD::FMA:
5537 case ISD::FMA:
lib/Target/AArch64/AArch64ISelLowering.cpp 242 setOperationAction(ISD::FMA, MVT::f128, Expand);
405 setOperationAction(ISD::FMA, MVT::f16, Promote);
437 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
456 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
669 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
8531 isOperationLegalOrCustom(ISD::FMA, VT) &&
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 887 case ISD::FMA:
2086 bool IsFMA = N->getOpcode() == ISD::FMA;
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 420 setOperationAction(ISD::FMA, VT, Expand);
519 case ISD::FMA:
2569 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
3702 case ISD::FMA:
lib/Target/AMDGPU/R600ISelLowering.cpp 222 setOperationAction(ISD::FMA, MVT::f32, Expand);
223 setOperationAction(ISD::FMA, MVT::f64, Expand);
lib/Target/AMDGPU/SIISelLowering.cpp 505 setOperationAction(ISD::FMA, MVT::f16, Legal);
611 setOperationAction(ISD::FMA, MVT::v2f16, Legal);
638 setOperationAction(ISD::FMA, MVT::v4f16, Custom);
710 setTargetDAGCombine(ISD::FMA);
767 (Opcode == ISD::FMA && Subtarget->hasFmaMixInsts())) &&
4065 case ISD::FMA:
7600 case ISD::FMA:
7731 SDValue Fma0 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0,
7734 SDValue Fma1 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, Fma0, ApproxRcp,
7740 SDValue Fma2 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Mul,
7743 SDValue Fma3 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, Fma2, Fma1, Mul, Fma2);
7745 SDValue Fma4 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Fma3,
7797 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One);
7799 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp);
7801 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One);
7805 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1);
7808 SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f64,
8569 case ISD::FMA:
8738 case ISD::FMA:
9424 return ISD::FMA;
9709 if (FMA.getOpcode() != ISD::FMA ||
9964 case ISD::FMA:
lib/Target/ARM/ARMISelLowering.cpp 795 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
895 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
896 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
939 setOperationAction(ISD::FMA, MVT::f64, Expand);
1315 setOperationAction(ISD::FMA, MVT::f64, Expand);
1316 setOperationAction(ISD::FMA, MVT::f32, Expand);
lib/Target/Hexagon/HexagonISelLowering.cpp 1427 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV,
1525 setOperationAction(ISD::FMA, MVT::f64, Expand);
1851 return isOperationLegalOrCustom(ISD::FMA, VT);
lib/Target/Mips/MipsISelLowering.cpp 448 setOperationAction(ISD::FMA, MVT::f32, Expand);
449 setOperationAction(ISD::FMA, MVT::f64, Expand);
lib/Target/Mips/MipsSEISelLowering.cpp 136 setOperationAction(ISD::FMA, MVT::f16, Promote);
391 setOperationAction(ISD::FMA, Ty, Legal);
1902 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
lib/Target/NVPTX/NVPTXISelLowering.cpp 536 for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) {
4438 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
lib/Target/PowerPC/PPCISelLowering.cpp 283 setOperationAction(ISD::FMA , MVT::f64, Expand);
284 setOperationAction(ISD::FMA , MVT::f32, Expand);
286 setOperationAction(ISD::FMA , MVT::f64, Legal);
287 setOperationAction(ISD::FMA , MVT::f32, Legal);
718 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
775 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
891 setOperationAction(ISD::FMA, MVT::f128, Legal);
7723 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
9673 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
9873 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
lib/Target/Sparc/SparcISelLowering.cpp 1620 setOperationAction(ISD::FMA , MVT::f128, Expand);
1625 setOperationAction(ISD::FMA , MVT::f64, Expand);
1630 setOperationAction(ISD::FMA , MVT::f32, Expand);
lib/Target/SystemZ/SystemZISelLowering.cpp 476 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
508 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
565 setOperationAction(ISD::FMA, MVT::f32, Legal);
566 setOperationAction(ISD::FMA, MVT::f64, Legal);
568 setOperationAction(ISD::FMA, MVT::f128, Legal);
570 setOperationAction(ISD::FMA, MVT::f128, Expand);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 93 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA})
lib/Target/X86/X86ISelLowering.cpp 624 setOperationAction(ISD::FMA, MVT::f64, Expand);
625 setOperationAction(ISD::FMA, MVT::f32, Expand);
657 setOperationAction(ISD::FMA, MVT::f80, Expand);
675 setOperationAction(ISD::FMA, MVT::f128, Expand);
755 setOperationAction(ISD::FMA, VT, Expand);
1184 setOperationAction(ISD::FMA, VT, Legal);
1374 setOperationAction(ISD::FMA, VT, Legal);
1855 setTargetDAGCombine(ISD::FMA);
33916 if (FMAdd.getOpcode() != ISD::FMA || FMSub.getOpcode() != X86ISD::FMSUB ||
36224 case ISD::FMA: // Begin 3 operands
41494 case ISD::FMA: Opcode = X86ISD::FNMADD; break;
41498 case X86ISD::FNMADD: Opcode = ISD::FMA; break;
41508 case ISD::FMA: Opcode = X86ISD::FMSUB; break;
41510 case X86ISD::FMSUB: Opcode = ISD::FMA; break;
41526 case ISD::FMA: Opcode = X86ISD::FNMSUB; break;
41532 case X86ISD::FNMSUB: Opcode = ISD::FMA; break;
41571 case ISD::FMA:
41606 case ISD::FMA:
41646 case ISD::FMA:
45018 case ISD::FMA: return combineFMA(N, DAG, DCI, Subtarget);
lib/Target/X86/X86IntrinsicsInfo.h 934 X86_INTRINSIC_DATA(avx512_vfmadd_f32, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
935 X86_INTRINSIC_DATA(avx512_vfmadd_f64, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
936 X86_INTRINSIC_DATA(avx512_vfmadd_pd_512, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
937 X86_INTRINSIC_DATA(avx512_vfmadd_ps_512, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),