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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc94049 /*213778*/ /*SwitchOpcode*/ 49, TARGET_VAL(ISD::FFLOOR),// ->213830
94361 /*214356*/ /*SwitchOpcode*/ 49, TARGET_VAL(ISD::FFLOOR),// ->214408
105903 /*236767*/ /*SwitchOpcode*/ 91, TARGET_VAL(ISD::FFLOOR),// ->236861
gen/lib/Target/AArch64/AArch64GenFastISel.inc 4278 case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc58256 /*127700*/ OPC_CheckOpcode, TARGET_VAL(ISD::FFLOOR),
74107 /*163865*/ OPC_CheckOpcode, TARGET_VAL(ISD::FFLOOR),
74124 /*163901*/ OPC_CheckOpcode, TARGET_VAL(ISD::FFLOOR),
74220 /*164146*/ OPC_CheckOpcode, TARGET_VAL(ISD::FFLOOR),
74786 /*165538*/ /*SwitchOpcode*/ 36|128,1/*164*/, TARGET_VAL(ISD::FFLOOR),// ->165706
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 9738 /* 37130*/ /*SwitchOpcode*/ 69, TARGET_VAL(ISD::FFLOOR),// ->37202
gen/lib/Target/ARM/ARMGenDAGISel.inc37100 /* 81635*/ /*SwitchOpcode*/ 78, TARGET_VAL(ISD::FFLOOR),// ->81716
37352 /* 82236*/ /*SwitchOpcode*/ 78, TARGET_VAL(ISD::FFLOOR),// ->82317
45149 /* 99914*/ /*SwitchOpcode*/ 88, TARGET_VAL(ISD::FFLOOR),// ->100005
gen/lib/Target/ARM/ARMGenFastISel.inc 2713 case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc71303 /*150358*/ /*SwitchOpcode*/ 61, TARGET_VAL(ISD::FFLOOR),// ->150422
gen/lib/Target/PowerPC/PPCGenDAGISel.inc38691 /* 97905*/ /*SwitchOpcode*/ 113, TARGET_VAL(ISD::FFLOOR),// ->98021
gen/lib/Target/PowerPC/PPCGenFastISel.inc 1701 case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc24742 /* 46779*/ /*SwitchOpcode*/ 33|128,1/*161*/, TARGET_VAL(ISD::FFLOOR),// ->46944
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc19156 /* 36580*/ /*SwitchOpcode*/ 21, TARGET_VAL(ISD::FFLOOR),// ->36604
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 966 case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0, Op0IsKill);
include/llvm/CodeGen/BasicTTIImpl.h 1252 ISDs.push_back(ISD::FFLOOR);
include/llvm/CodeGen/TargetLowering.h 964 case ISD::STRICT_FFLOOR: EqOpc = ISD::FFLOOR; break;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1579 case ISD::FFLOOR: return visitFFLOOR(N);
13138 case ISD::FFLOOR:
13152 return DAG.getNode(ISD::FFLOOR, SDLoc(N), VT, N0);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3926 case ISD::FFLOOR:
4386 case ISD::FFLOOR:
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 78 case ISD::FFLOOR: R = SoftenFloatRes_FFLOOR(N); break;
1151 case ISD::FFLOOR: ExpandFloatRes_FFLOOR(N, Lo, Hi); break;
2060 case ISD::FFLOOR:
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 427 case ISD::FFLOOR:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 85 case ISD::FFLOOR:
897 case ISD::FFLOOR:
2858 case ISD::FFLOOR:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 4013 case ISD::FFLOOR:
4376 case ISD::FFLOOR: {
4432 case ISD::FFLOOR:
7777 case ISD::STRICT_FFLOOR: NewOpc = ISD::FFLOOR; break;
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 6040 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
7619 if (visitUnaryFloatCall(I, ISD::FFLOOR))
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 201 case ISD::FFLOOR: return "ffloor";
lib/CodeGen/TargetLoweringBase.cpp 772 setOperationAction(ISD::FFLOOR, VT, Expand);
lib/Target/AArch64/AArch64ISelLowering.cpp 410 setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
444 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
455 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
474 setOperationAction(ISD::FFLOOR, Ty, Legal);
492 setOperationAction(ISD::FFLOOR, MVT::f16, Legal);
668 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
782 setOperationAction(ISD::FFLOOR, Ty, Legal);
792 setOperationAction(ISD::FFLOOR, Ty, Legal);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 255 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
417 setOperationAction(ISD::FFLOOR, VT, Expand);
1144 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
2566 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
lib/Target/AMDGPU/R600ISelLowering.cpp 155 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
lib/Target/AMDGPU/SIISelLowering.cpp 422 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
425 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
8593 case ISD::FFLOOR:
8737 case ISD::FFLOOR:
lib/Target/ARM/ARMISelLowering.cpp 794 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
814 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
830 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
959 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
1343 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1359 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
lib/Target/Hexagon/HexagonISelLowering.cpp 1431 ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR,
lib/Target/Mips/MipsSEISelLowering.cpp 143 setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
lib/Target/NVPTX/NVPTXISelLowering.cpp 548 for (const auto &Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FRINT,
lib/Target/PowerPC/PPCISelLowering.cpp 236 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
312 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
317 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
641 setOperationAction(ISD::FFLOOR, VT, Expand);
702 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
766 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
901 setOperationAction(ISD::FFLOOR, MVT::f128, Legal);
1050 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1055 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
lib/Target/PowerPC/PPCTargetTransformInfo.cpp 330 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
382 Opcode = ISD::FFLOOR; break;
lib/Target/SystemZ/SystemZISelLowering.cpp 425 setOperationAction(ISD::FFLOOR, VT, Legal);
482 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
514 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 98 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT})
184 for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT,
lib/Target/X86/X86ISelDAGToDAG.cpp 872 case ISD::FFLOOR:
882 case ISD::FFLOOR: Imm = 0x9; break;
5194 case ISD::FFLOOR:
5208 case ISD::FFLOOR: Imm = 0x9; break;
lib/Target/X86/X86ISelLowering.cpp 652 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
756 setOperationAction(ISD::FFLOOR, VT, Expand);
1032 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
1108 setOperationAction(ISD::FFLOOR, VT, Legal);
1423 setOperationAction(ISD::FFLOOR, VT, Legal);
1831 {ISD::FCEIL, ISD::FCOS, ISD::FEXP, ISD::FFLOOR, ISD::FREM, ISD::FLOG,
36247 case ISD::FFLOOR: