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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc104801 /*234639*/ /*SwitchOpcode*/ 72|128,2/*328*/, TARGET_VAL(ISD::FDIV),// ->234971
gen/lib/Target/AArch64/AArch64GenFastISel.inc 7724 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 9192 /* 35046*/ /*SwitchOpcode*/ 83|128,5/*723*/, TARGET_VAL(ISD::FDIV),// ->35773
gen/lib/Target/ARM/ARMGenDAGISel.inc44704 /* 98890*/ /*SwitchOpcode*/ 64, TARGET_VAL(ISD::FDIV),// ->98957
gen/lib/Target/ARM/ARMGenFastISel.inc 5164 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/Mips/MipsGenDAGISel.inc27463 /* 51970*/ /*SwitchOpcode*/ 113, TARGET_VAL(ISD::FDIV),// ->52086
gen/lib/Target/Mips/MipsGenFastISel.inc 3411 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc69697 /*147233*/ /*SwitchOpcode*/ 41|128,2/*297*/, TARGET_VAL(ISD::FDIV),// ->147534
gen/lib/Target/PowerPC/PPCGenDAGISel.inc38094 /* 96799*/ /*SwitchOpcode*/ 114, TARGET_VAL(ISD::FDIV),// ->96916
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3236 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc13544 /* 25344*/ /*SwitchOpcode*/ 102, TARGET_VAL(ISD::FDIV),// ->25449
gen/lib/Target/Sparc/SparcGenDAGISel.inc 3259 /* 6022*/ /*SwitchOpcode*/ 36, TARGET_VAL(ISD::FDIV),// ->6061
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc23772 /* 44803*/ /*SwitchOpcode*/ 25|128,1/*153*/, TARGET_VAL(ISD::FDIV),// ->44960
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc18956 /* 36194*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::FDIV),// ->36245
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 1906 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc64501 /*136340*/ /*SwitchOpcode*/ 29|128,11/*1437*/, TARGET_VAL(ISD::FDIV),// ->137781
130796 /*268545*/ /*SwitchOpcode*/ 3|128,1/*131*/, TARGET_VAL(ISD::FDIV),// ->268680
136377 /*279795*/ /*SwitchOpcode*/ 1|128,1/*129*/, TARGET_VAL(ISD::FDIV),// ->279928
141651 /*290436*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FDIV),// ->290473
143542 /*294027*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FDIV),// ->294064
150070 /*306394*/ /*SwitchOpcode*/ 76, TARGET_VAL(ISD::FDIV),// ->306473
153380 /*312724*/ /*SwitchOpcode*/ 74, TARGET_VAL(ISD::FDIV),// ->312801
156672 /*318981*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::FDIV),// ->319003
157953 /*321328*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::FDIV),// ->321349
164590 /*333962*/ /*SwitchOpcode*/ 3|128,1/*131*/, TARGET_VAL(ISD::FDIV),// ->334097
169884 /*344655*/ /*SwitchOpcode*/ 1|128,1/*129*/, TARGET_VAL(ISD::FDIV),// ->344788
174667 /*354413*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FDIV),// ->354450
175989 /*356943*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FDIV),// ->356980
181254 /*367097*/ /*SwitchOpcode*/ 2|128,1/*130*/, TARGET_VAL(ISD::FDIV),// ->367231
185501 /*375203*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::FDIV),// ->375225
186203 /*376479*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::FDIV),// ->376500
233699 /*476568*/ /*SwitchOpcode*/ 93, TARGET_VAL(ISD::FDIV),// ->476664
235167 /*479656*/ /*SwitchOpcode*/ 85, TARGET_VAL(ISD::FDIV),// ->479744
236856 /*483198*/ /*SwitchOpcode*/ 87, TARGET_VAL(ISD::FDIV),// ->483288
237843 /*485327*/ /*SwitchOpcode*/ 82, TARGET_VAL(ISD::FDIV),// ->485412
240131 /*490098*/ /*SwitchOpcode*/ 93, TARGET_VAL(ISD::FDIV),// ->490194
241599 /*493186*/ /*SwitchOpcode*/ 85, TARGET_VAL(ISD::FDIV),// ->493274
243373 /*496905*/ /*SwitchOpcode*/ 87, TARGET_VAL(ISD::FDIV),// ->496995
244361 /*499036*/ /*SwitchOpcode*/ 82, TARGET_VAL(ISD::FDIV),// ->499121
gen/lib/Target/X86/X86GenFastISel.inc13514 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
include/llvm/CodeGen/TargetLowering.h 944 case ISD::STRICT_FDIV: EqOpc = ISD::FDIV; break;
2309 case ISD::FDIV:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1566 case ISD::FDIV: return visitFDIV(N);
12480 if (U->getOpcode() == ISD::FDIV && U->getOperand(1) == N1) {
12495 SDValue Reciprocal = DAG.getNode(ISD::FDIV, DL, VT, FPOne, N1, Flags);
12530 return DAG.getNode(ISD::FDIV, SDLoc(N), VT, N0, N1, Flags);
12595 RV = DAG.getNode(ISD::FDIV, SDLoc(N1), VT, RV, OtherOp, Flags);
12610 ISD::FDIV, SDLoc(N), VT,
lib/CodeGen/SelectionDAG/FastISel.cpp 1815 return selectBinaryOp(I, ISD::FDIV);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 4007 case ISD::FDIV:
4349 case ISD::FDIV:
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 75 case ISD::FDIV: R = SoftenFloatRes_FDIV(N); break;
1148 case ISD::FDIV: ExpandFloatRes_FDIV(N, Lo, Hi); break;
2075 case ISD::FDIV:
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 373 case ISD::FDIV:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 112 case ISD::FDIV:
943 case ISD::FDIV:
2759 case ISD::FDIV:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 4000 case ISD::FDIV:
4998 case ISD::FDIV:
5024 case ISD::FDIV:
5122 case ISD::FDIV:
7173 if (Opcode == ISD::FMUL || Opcode == ISD::FDIV)
7757 case ISD::STRICT_FDIV: NewOpc = ISD::FDIV; break;
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 5379 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h 685 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 252 case ISD::FDIV: return "fdiv";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 2484 case ISD::FDIV:
5413 case ISD::FDIV:
5520 case ISD::FDIV:
lib/CodeGen/TargetLoweringBase.cpp 1600 case FDiv: return ISD::FDIV;
lib/Target/AArch64/AArch64ISelLowering.cpp 241 setOperationAction(ISD::FDIV, MVT::f128, Custom);
404 setOperationAction(ISD::FDIV, MVT::f16, Promote);
424 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
430 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
454 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
597 setTargetDAGCombine(ISD::FDIV);
667 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
3014 case ISD::FDIV:
11735 case ISD::FDIV:
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 409 setOperationAction(ISD::FDIV, VT, Expand);
562 case ISD::FDIV:
2026 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp 400 case ISD::FDIV:
lib/Target/AMDGPU/SIISelLowering.cpp 429 setOperationAction(ISD::FDIV, MVT::f32, Custom);
430 setOperationAction(ISD::FDIV, MVT::f64, Custom);
502 setOperationAction(ISD::FDIV, MVT::f16, Custom);
4030 case ISD::FDIV: return LowerFDIV(Op, DAG);
8567 case ISD::FDIV:
8741 case ISD::FDIV:
lib/Target/ARM/ARMISelLowering.cpp 203 setOperationAction(ISD::FDIV, VT, Expand);
333 setOperationAction(ISD::FDIV, VT, Expand);
768 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
907 setTargetDAGCombine(ISD::FDIV);
940 setOperationAction(ISD::FDIV, MVT::f64, Expand);
14446 case ISD::FDIV:
lib/Target/Hexagon/HexagonISelLowering.cpp 1383 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
1427 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV,
lib/Target/Mips/MipsSEISelLowering.cpp 134 setOperationAction(ISD::FDIV, MVT::f16, Promote);
388 setOperationAction(ISD::FDIV, Ty, Legal);
1867 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
lib/Target/NVPTX/NVPTXISelLowering.cpp 571 for (const auto &Op : {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS,
lib/Target/PowerPC/PPCISelLowering.cpp 629 setOperationAction(ISD::FDIV, VT, Expand);
721 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
777 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
885 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1068 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1071 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
1074 setOperationAction(ISD::FDIV, MVT::v4f64, Expand);
1077 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
1144 setTargetDAGCombine(ISD::FDIV);
lib/Target/Sparc/SparcISelLowering.cpp 1714 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1739 setOperationAction(ISD::FDIV, MVT::f128, Custom);
1791 setOperationAction(ISD::FDIV, MVT::f32, Promote);
3044 case ISD::FDIV: return LowerF128Op(Op, DAG,
lib/Target/SystemZ/SystemZISelLowering.cpp 477 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
509 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 195 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
lib/Target/X86/X86ISelLowering.cpp 673 setOperationAction(ISD::FDIV, MVT::f128, Custom);
27712 case ISD::FDIV: return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
33592 Opcode1 == ISD::FDIV) {
36229 case ISD::FDIV:
lib/Target/X86/X86IntrinsicsInfo.h 448 X86_INTRINSIC_DATA(avx512_div_pd_512, INTR_TYPE_2OP, ISD::FDIV, X86ISD::FDIV_RND),
449 X86_INTRINSIC_DATA(avx512_div_ps_512, INTR_TYPE_2OP, ISD::FDIV, X86ISD::FDIV_RND),
lib/Target/X86/X86TargetTransformInfo.cpp 185 { ISD::FDIV, MVT::f32, 18 }, // divss
186 { ISD::FDIV, MVT::v4f32, 35 }, // divps
187 { ISD::FDIV, MVT::f64, 33 }, // divsd
188 { ISD::FDIV, MVT::v2f64, 65 }, // divpd
203 { ISD::FDIV, MVT::f32, 17 }, // divss
204 { ISD::FDIV, MVT::v4f32, 39 }, // divps
205 { ISD::FDIV, MVT::f64, 32 }, // divsd
206 { ISD::FDIV, MVT::v2f64, 69 }, // divpd
701 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/
702 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/
703 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/
704 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/
705 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/
706 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/
738 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/
739 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/
740 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/
741 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/
742 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/
743 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/
766 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/
767 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/
768 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/
769 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/
831 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/
832 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/
833 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/
834 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/
848 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/
849 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/