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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc94020 /*213726*/ /*SwitchOpcode*/ 49, TARGET_VAL(ISD::FCEIL),// ->213778
94332 /*214304*/ /*SwitchOpcode*/ 49, TARGET_VAL(ISD::FCEIL),// ->214356
105954 /*236861*/ /*SwitchOpcode*/ 91, TARGET_VAL(ISD::FCEIL),// ->236955
gen/lib/Target/AArch64/AArch64GenFastISel.inc 4277 case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc76071 /*168893*/ /*SwitchOpcode*/ 52, TARGET_VAL(ISD::FCEIL),// ->168948
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 9698 /* 36986*/ /*SwitchOpcode*/ 69, TARGET_VAL(ISD::FCEIL),// ->37058
gen/lib/Target/ARM/ARMGenDAGISel.inc37064 /* 81554*/ /*SwitchOpcode*/ 78, TARGET_VAL(ISD::FCEIL),// ->81635
37316 /* 82155*/ /*SwitchOpcode*/ 78, TARGET_VAL(ISD::FCEIL),// ->82236
45108 /* 99823*/ /*SwitchOpcode*/ 88, TARGET_VAL(ISD::FCEIL),// ->99914
gen/lib/Target/ARM/ARMGenFastISel.inc 2712 case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc71272 /*150294*/ /*SwitchOpcode*/ 61, TARGET_VAL(ISD::FCEIL),// ->150358
gen/lib/Target/PowerPC/PPCGenDAGISel.inc38754 /* 98021*/ /*SwitchOpcode*/ 113, TARGET_VAL(ISD::FCEIL),// ->98137
gen/lib/Target/PowerPC/PPCGenFastISel.inc 1700 case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc24899 /* 47124*/ /*SwitchOpcode*/ 33|128,1/*161*/, TARGET_VAL(ISD::FCEIL),// ->47289
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc19143 /* 36556*/ /*SwitchOpcode*/ 21, TARGET_VAL(ISD::FCEIL),// ->36580
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 965 case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0, Op0IsKill);
include/llvm/CodeGen/BasicTTIImpl.h 1255 ISDs.push_back(ISD::FCEIL);
include/llvm/CodeGen/TargetLowering.h 963 case ISD::STRICT_FCEIL: EqOpc = ISD::FCEIL; break;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1584 case ISD::FCEIL: return visitFCEIL(N);
13117 return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0);
13139 case ISD::FCEIL:
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3932 case ISD::FCEIL:
4387 case ISD::FCEIL:
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 72 case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break;
1145 case ISD::FCEIL: ExpandFloatRes_FCEIL(N, Lo, Hi); break;
2056 case ISD::FCEIL:
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 422 case ISD::FCEIL:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 81 case ISD::FCEIL:
893 case ISD::FCEIL:
2854 case ISD::FCEIL:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 4014 case ISD::FCEIL:
4364 case ISD::FCEIL: {
4430 case ISD::FCEIL:
7776 case ISD::STRICT_FCEIL: NewOpc = ISD::FCEIL; break;
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 6041 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
7631 if (visitUnaryFloatCall(I, ISD::FCEIL))
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 203 case ISD::FCEIL: return "fceil";
lib/CodeGen/TargetLoweringBase.cpp 774 setOperationAction(ISD::FCEIL, VT, Expand);
lib/Target/AArch64/AArch64ISelLowering.cpp 408 setOperationAction(ISD::FCEIL, MVT::f16, Promote);
445 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
452 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
476 setOperationAction(ISD::FCEIL, Ty, Legal);
493 setOperationAction(ISD::FCEIL, MVT::f16, Legal);
664 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
784 setOperationAction(ISD::FCEIL, Ty, Legal);
794 setOperationAction(ISD::FCEIL, Ty, Legal);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 250 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
407 setOperationAction(ISD::FCEIL, VT, Expand);
1139 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
lib/Target/AMDGPU/R600ISelLowering.cpp 152 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
lib/Target/AMDGPU/SIISelLowering.cpp 416 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
419 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
8588 case ISD::FCEIL:
8736 case ISD::FCEIL:
lib/Target/ARM/ARMISelLowering.cpp 790 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
810 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
826 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
955 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
1344 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1360 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
lib/Target/Hexagon/HexagonISelLowering.cpp 1430 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC,
lib/Target/Mips/MipsSEISelLowering.cpp 139 setOperationAction(ISD::FCEIL, MVT::f16, Promote);
lib/Target/NVPTX/NVPTXISelLowering.cpp 548 for (const auto &Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FRINT,
lib/Target/PowerPC/PPCISelLowering.cpp 237 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
313 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
318 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
642 setOperationAction(ISD::FCEIL, VT, Expand);
703 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
767 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
902 setOperationAction(ISD::FCEIL, MVT::f128, Legal);
1051 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1056 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
lib/Target/PowerPC/PPCTargetTransformInfo.cpp 331 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
390 Opcode = ISD::FCEIL; break;
lib/Target/SystemZ/SystemZISelLowering.cpp 426 setOperationAction(ISD::FCEIL, VT, Legal);
483 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
515 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 98 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT})
184 for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT,
lib/Target/X86/X86ISelDAGToDAG.cpp 871 case ISD::FCEIL:
881 case ISD::FCEIL: Imm = 0xA; break;
5193 case ISD::FCEIL:
5207 case ISD::FCEIL: Imm = 0xA; break;
lib/Target/X86/X86ISelLowering.cpp 653 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
757 setOperationAction(ISD::FCEIL, VT, Expand);
1033 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
1109 setOperationAction(ISD::FCEIL, VT, Legal);
1424 setOperationAction(ISD::FCEIL, VT, Legal);
1831 {ISD::FCEIL, ISD::FCOS, ISD::FEXP, ISD::FFLOOR, ISD::FREM, ISD::FLOG,
36243 case ISD::FCEIL: