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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc105498 /*236018*/ /*SwitchOpcode*/ 82|128,1/*210*/, TARGET_VAL(ISD::FABS),// ->236232
gen/lib/Target/AArch64/AArch64GenFastISel.inc 4276 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc74843 /*165714*/ OPC_CheckOpcode, TARGET_VAL(ISD::FABS),
74966 /*166059*/ /*SwitchOpcode*/ 46, TARGET_VAL(ISD::FABS),// ->166108
75090 /*166321*/ /*SwitchOpcode*/ 71|128,1/*199*/, TARGET_VAL(ISD::FABS),// ->166524
gen/lib/Target/AMDGPU/R600GenDAGISel.inc10685 /* 40853*/ /*SwitchOpcode*/ 10, TARGET_VAL(ISD::FABS),// ->40866
gen/lib/Target/ARM/ARMGenDAGISel.inc44526 /* 98440*/ /*SwitchOpcode*/ 106|128,2/*362*/, TARGET_VAL(ISD::FABS),// ->98806
gen/lib/Target/ARM/ARMGenFastISel.inc 2711 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc68396 /*132417*/ /*SwitchOpcode*/ 71, TARGET_VAL(ISD::FABS),// ->132491
gen/lib/Target/Mips/MipsGenDAGISel.inc27353 /* 51778*/ /*SwitchOpcode*/ 93, TARGET_VAL(ISD::FABS),// ->51874
gen/lib/Target/Mips/MipsGenFastISel.inc 1198 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc70903 /*149516*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FABS),// ->149553
gen/lib/Target/PowerPC/PPCGenDAGISel.inc36011 /* 92542*/ /*SwitchOpcode*/ 26, TARGET_VAL(ISD::FABS),// ->92571
36084 /* 92676*/ /*SwitchOpcode*/ 52, TARGET_VAL(ISD::FABS),// ->92731
36189 /* 92861*/ /*SwitchOpcode*/ 26, TARGET_VAL(ISD::FABS),// ->92890
36270 /* 93009*/ /*SwitchOpcode*/ 26, TARGET_VAL(ISD::FABS),// ->93038
38331 /* 97223*/ /*SwitchOpcode*/ 118, TARGET_VAL(ISD::FABS),// ->97344
gen/lib/Target/PowerPC/PPCGenFastISel.inc 1699 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc13340 /* 24924*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::FABS),// ->24954
gen/lib/Target/Sparc/SparcGenDAGISel.inc 3179 /* 5870*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FABS),// ->5907
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc23967 /* 45176*/ /*SwitchOpcode*/ 71, TARGET_VAL(ISD::FABS),// ->45250
24138 /* 45479*/ /*SwitchOpcode*/ 26, TARGET_VAL(ISD::FABS),// ->45508
25721 /* 48909*/ /*SwitchOpcode*/ 92, TARGET_VAL(ISD::FABS),// ->49004
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc19007 /* 36291*/ /*SwitchOpcode*/ 43, TARGET_VAL(ISD::FABS),// ->36337
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 964 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc75444 /*159145*/ /*SwitchOpcode*/ 37, TARGET_VAL(ISD::FABS),// ->159185
gen/lib/Target/X86/X86GenFastISel.inc 5912 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill);
include/llvm/CodeGen/BasicTTIImpl.h 1233 ISDs.push_back(ISD::FABS);
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1578 case ISD::FABS: return visitFABS(N);
10916 FPOpcode = ISD::FABS;
10924 FPOpcode = ISD::FABS;
11034 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
11050 assert(N0.getOpcode() == ISD::FABS);
11068 assert(N0.getOpcode() == ISD::FABS);
12273 TLI.isOperationLegal(ISD::FABS, VT)) {
12306 DAG.getNode(ISD::FABS, DL, VT, X));
12308 return DAG.getNode(ISD::FABS, DL, VT, X);
12680 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
12681 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
12685 DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0));
12692 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
12697 if (N1.getOpcode() == ISD::FABS)
12698 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
13259 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
13262 if (N0.getOpcode() == ISD::FABS)
13268 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0.getOperand(0));
20449 SDValue Fabs = DAG.getNode(ISD::FABS, DL, VT, Op);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 1518 if (TLI.isOperationLegalOrCustom(ISD::FABS, FloatVT) &&
1520 SDValue AbsValue = DAG.getNode(ISD::FABS, DL, FloatVT, Mag);
3085 case ISD::FABS:
4399 case ISD::FABS:
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 67 case ISD::FABS: R = SoftenFloatRes_FABS(N); break;
1140 case ISD::FABS: ExpandFloatRes_FABS(N, Lo, Hi); break;
1201 Hi = DAG.getNode(ISD::FABS, dl, Tmp.getValueType(), Tmp);
2054 case ISD::FABS:
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 404 case ISD::FABS:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 80 case ISD::FABS:
892 case ISD::FABS:
2853 case ISD::FABS:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 4022 case ISD::FABS:
4361 case ISD::FABS:
4429 case ISD::FABS:
4661 case ISD::FABS:
4663 return getNode(ISD::FABS, DL, VT, Operand.getOperand(0));
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 6037 case Intrinsic::fabs: Opcode = ISD::FABS; break;
7580 if (visitUnaryFloatCall(I, ISD::FABS))
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 181 case ISD::FABS: return "fabs";
lib/Target/AArch64/AArch64ISelLowering.cpp 237 setOperationAction(ISD::FABS, MVT::f128, Expand);
407 setOperationAction(ISD::FABS, MVT::f16, Promote);
434 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
450 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
662 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 2388 if (Src.getOpcode() == ISD::FABS) {
2423 if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG)
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 254 setOperationAction(ISD::FABS, MVT::f32, Legal);
403 setOperationAction(ISD::FABS, VT, Expand);
503 setTargetDAGCombine(ISD::FABS);
1597 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1600 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
2137 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
2172 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff);
3490 if ((LHS.getOpcode() == ISD::FABS && RHS.getOpcode() == ISD::FABS) ||
3490 if ((LHS.getOpcode() == ISD::FABS && RHS.getOpcode() == ISD::FABS) ||
3497 if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) {
3504 if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS) {
3518 if (LHS.getOpcode() == ISD::FABS && Opc == ISD::FMUL)
3980 case ISD::FABS:
lib/Target/AMDGPU/SIISelLowering.cpp 583 setOperationAction(ISD::FABS, MVT::v2f16, Legal);
653 setOperationAction(ISD::FABS, MVT::v4f16, Custom);
666 setOperationAction(ISD::FABS, MVT::v2f16, Custom);
4058 case ISD::FABS:
4355 case ISD::FABS: {
7635 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
8298 if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X)
8575 case ISD::FABS:
8769 case ISD::FABS:
9259 Vec.getOpcode() == ISD::FABS) && allUsesHaveSourceMods(N)) {
9841 if ((CC == ISD::SETOEQ || CC == ISD::SETONE) && LHS.getOpcode() == ISD::FABS) {
lib/Target/ARM/ARMISelLowering.cpp 779 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
945 setOperationAction(ISD::FABS, MVT::f64, Expand);
lib/Target/Hexagon/HexagonISelLowering.cpp 1428 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
lib/Target/Mips/MipsISelLowering.cpp 364 setOperationAction(ISD::FABS, MVT::f32, Custom);
365 setOperationAction(ISD::FABS, MVT::f64, Custom);
1232 case ISD::FABS: return lowerFABS(Op, DAG);
lib/Target/Mips/MipsSEISelLowering.cpp 138 setOperationAction(ISD::FABS, MVT::f16, Promote);
386 setOperationAction(ISD::FABS, Ty, Legal);
lib/Target/NVPTX/NVPTXISelLowering.cpp 572 ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM}) {
2102 SDValue AbsA = DAG.getNode(ISD::FABS, SL, VT, A);
2143 SDValue AbsA = DAG.getNode(ISD::FABS, SL, VT, A);
lib/Target/PowerPC/PPCISelLowering.cpp 640 setOperationAction(ISD::FABS, VT, Expand);
853 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
854 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
963 setOperationAction(ISD::FABS , MVT::v4f64, Legal);
1008 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
lib/Target/RISCV/RISCVISelLowering.cpp 953 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) ||
967 assert(Op0.getOpcode() == ISD::FABS);
1001 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) ||
1012 assert(Op0.getOpcode() == ISD::FABS);
lib/Target/Sparc/SparcISelLowering.cpp 1613 setOperationAction(ISD::FABS, MVT::f64, Custom);
1720 setOperationAction(ISD::FABS, MVT::f128, Legal);
1723 setOperationAction(ISD::FABS, MVT::f128, Custom);
1742 setOperationAction(ISD::FABS, MVT::f128, Custom);
2694 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2839 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
3048 case ISD::FABS:
lib/Target/SystemZ/SystemZISelLowering.cpp 478 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
510 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
lib/Target/X86/X86ISelLowering.cpp 531 setOperationAction(ISD::FABS, VT, Custom);
561 setOperationAction(ISD::FABS , MVT::f32, Custom);
677 setOperationAction(ISD::FABS, MVT::f128, Custom);
816 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
869 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
1114 setOperationAction(ISD::FABS, VT, Custom);
1373 setOperationAction(ISD::FABS, VT, Custom);
19741 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
19744 bool IsFABS = (Op.getOpcode() == ISD::FABS);
19783 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
27713 case ISD::FABS:
36240 case ISD::FABS: // Begin 1 operand