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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc112448 /*250622*/ /*SwitchOpcode*/ 29, TARGET_VAL(ISD::CTPOP),// ->250654
gen/lib/Target/AArch64/AArch64GenFastISel.inc 4275 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc28161 /* 59043*/ OPC_CheckOpcode, TARGET_VAL(ISD::CTPOP),
28180 /* 59075*/ OPC_CheckOpcode, TARGET_VAL(ISD::CTPOP),
28251 /* 59226*/ /*SwitchOpcode*/ 17, TARGET_VAL(ISD::CTPOP),// ->59246
28326 /* 59382*/ /*SwitchOpcode*/ 16, TARGET_VAL(ISD::CTPOP),// ->59401
28503 /* 59749*/ OPC_CheckOpcode, TARGET_VAL(ISD::CTPOP),
28517 /* 59773*/ OPC_CheckOpcode, TARGET_VAL(ISD::CTPOP),
62862 /*137141*/ /*SwitchOpcode*/ 97, TARGET_VAL(ISD::CTPOP),// ->137241
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 8717 /* 33460*/ /*SwitchOpcode*/ 71, TARGET_VAL(ISD::CTPOP),// ->33534
gen/lib/Target/ARM/ARMGenDAGISel.inc52793 /*117830*/ /*SwitchOpcode*/ 45, TARGET_VAL(ISD::CTPOP),// ->117878
gen/lib/Target/ARM/ARMGenFastISel.inc 2710 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc68104 /*131725*/ /*SwitchOpcode*/ 86|128,3/*470*/, TARGET_VAL(ISD::CTPOP),// ->132199
gen/lib/Target/Lanai/LanaiGenDAGISel.inc 1266 /* 2302*/ /*SwitchOpcode*/ 8, TARGET_VAL(ISD::CTPOP),// ->2313
gen/lib/Target/Mips/MipsGenDAGISel.inc25620 /* 48522*/ /*SwitchOpcode*/ 81, TARGET_VAL(ISD::CTPOP),// ->48606
gen/lib/Target/Mips/MipsGenFastISel.inc 1197 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc68428 /*144699*/ /*SwitchOpcode*/ 13, TARGET_VAL(ISD::CTPOP),// ->144715
68535 /*144916*/ OPC_SwitchOpcode /*2 cases */, 26, TARGET_VAL(ISD::CTPOP),// ->144946
69464 /*146789*/ /*SwitchOpcode*/ 69, TARGET_VAL(ISD::CTPOP),// ->146861
gen/lib/Target/PowerPC/PPCGenDAGISel.inc28552 /* 68594*/ /*SwitchOpcode*/ 77, TARGET_VAL(ISD::CTPOP),// ->68674
gen/lib/Target/PowerPC/PPCGenFastISel.inc 1697 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/Sparc/SparcGenDAGISel.inc 2997 /* 5537*/ /*SwitchOpcode*/ 38, TARGET_VAL(ISD::CTPOP),// ->5578
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc21451 /* 40300*/ /*SwitchOpcode*/ 73, TARGET_VAL(ISD::CTPOP),// ->40376
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc18411 /* 35280*/ /*SwitchOpcode*/ 25, TARGET_VAL(ISD::CTPOP),// ->35308
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 962 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc40950 /* 85592*/ /*SwitchOpcode*/ 41|128,8/*1065*/, TARGET_VAL(ISD::CTPOP),// ->86661
80138 /*168167*/ /*SwitchOpcode*/ 5|128,1/*133*/, TARGET_VAL(ISD::CTPOP),// ->168304
85086 /*178201*/ /*SwitchOpcode*/ 1|128,1/*129*/, TARGET_VAL(ISD::CTPOP),// ->178334
90862 /*189416*/ /*SwitchOpcode*/ 9|128,1/*137*/, TARGET_VAL(ISD::CTPOP),// ->189557
96944 /*201886*/ /*SwitchOpcode*/ 5|128,1/*133*/, TARGET_VAL(ISD::CTPOP),// ->202023
103981 /*215643*/ /*SwitchOpcode*/ 36|128,1/*164*/, TARGET_VAL(ISD::CTPOP),// ->215811
111123 /*230415*/ /*SwitchOpcode*/ 31|128,1/*159*/, TARGET_VAL(ISD::CTPOP),// ->230578
117429 /*242664*/ /*SwitchOpcode*/ 1|128,1/*129*/, TARGET_VAL(ISD::CTPOP),// ->242797
119461 /*246601*/ /*SwitchOpcode*/ 65, TARGET_VAL(ISD::CTPOP),// ->246669
122548 /*252835*/ /*SwitchOpcode*/ 120, TARGET_VAL(ISD::CTPOP),// ->252958
125423 /*258004*/ /*SwitchOpcode*/ 60, TARGET_VAL(ISD::CTPOP),// ->258067
127738 /*262571*/ /*SwitchOpcode*/ 57, TARGET_VAL(ISD::CTPOP),// ->262631
146301 /*299109*/ OPC_CheckOpcode, TARGET_VAL(ISD::CTPOP),
148109 /*302632*/ /*SwitchOpcode*/ 57, TARGET_VAL(ISD::CTPOP),// ->302692
160282 /*325538*/ /*SwitchOpcode*/ 41, TARGET_VAL(ISD::CTPOP),// ->325582
161926 /*328760*/ /*SwitchOpcode*/ 39, TARGET_VAL(ISD::CTPOP),// ->328802
177804 /*360351*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::CTPOP),// ->360373
178685 /*362016*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::CTPOP),// ->362037
187625 /*379116*/ /*SwitchOpcode*/ 41, TARGET_VAL(ISD::CTPOP),// ->379160
188352 /*380559*/ /*SwitchOpcode*/ 39, TARGET_VAL(ISD::CTPOP),// ->380601
188820 /*381415*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::CTPOP),// ->381437
189120 /*381985*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::CTPOP),// ->382006
gen/lib/Target/X86/X86GenFastISel.inc 5909 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill);
include/llvm/CodeGen/BasicTTIImpl.h 1452 ISDs.push_back(ISD::CTPOP);
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1545 case ISD::CTPOP: return visitCTPOP(N);
8113 return DAG.getNode(ISD::CTPOP, SDLoc(N), VT, N0);
9684 if (CtPop.getOpcode() != ISD::CTPOP || !CtPop.hasOneUse())
9689 if (TLI.isOperationLegalOrCustom(ISD::CTPOP, CtPop.getValueType()) ||
9690 !TLI.isOperationLegalOrCustom(ISD::CTPOP, VT))
9696 return DAG.getNode(ISD::CTPOP, DL, VT, NewZext);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2664 case ISD::CTPOP:
4142 case ISD::CTPOP:
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 65 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
446 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
1695 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
2516 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
2517 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 392 case ISD::CTPOP:
800 case ISD::CTPOP:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 77 case ISD::CTPOP:
891 case ISD::CTPOP:
2019 case ISD::CTPOP:
2890 case ISD::CTPOP:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 2912 case ISD::CTPOP: {
4329 case ISD::CTPOP:
4449 case ISD::CTPOP: {
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 6221 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 386 case ISD::CTPOP: return "ctpop";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 3112 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
3129 if (C1 == 1 && !isOperationLegalOrCustom(ISD::CTPOP, CTVT) &&
6248 !isOperationLegalOrCustom(ISD::CTPOP, VT) ||
6268 Result = DAG.getNode(ISD::CTPOP, dl, VT, Op);
6300 (!isOperationLegalOrCustom(ISD::CTPOP, VT) &&
6316 if (isOperationLegal(ISD::CTLZ, VT) && !isOperationLegal(ISD::CTPOP, VT)) {
6323 Result = DAG.getNode(ISD::CTPOP, dl, VT, Tmp);
6761 Increment = DAG.getNode(ISD::CTPOP, DL, MaskIntVT, MaskInIntReg);
lib/Target/AArch64/AArch64ISelLowering.cpp 319 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
320 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
861 setOperationAction(ISD::CTPOP, VT, Custom);
3049 case ISD::CTPOP:
4910 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
4926 Val = DAG.getNode(ISD::CTPOP, DL, VT8Bit, Val);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 391 setOperationAction(ISD::CTPOP, VT, Expand);
lib/Target/AMDGPU/R600ISelLowering.cpp 238 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
241 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
lib/Target/AMDGPU/SIISelLowering.cpp 377 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
380 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
459 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
lib/Target/ARM/ARMISelLowering.cpp 278 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
863 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
864 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
865 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
866 setOperationAction(ISD::CTPOP, MVT::v1i64, Custom);
867 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
1076 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
5907 return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
5935 return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
5958 Res = DAG.getNode(ISD::CTPOP, DL, VT8Bit, Res);
9189 case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
lib/Target/AVR/AVRISelLowering.cpp 180 setOperationAction(ISD::CTPOP, VT, Expand);
lib/Target/BPF/BPFISelLowering.cpp 99 setOperationAction(ISD::CTPOP, VT, Expand);
lib/Target/Hexagon/HexagonISelLowering.cpp 1358 setOperationAction(ISD::CTPOP, MVT::i8, Promote);
1359 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
1360 setOperationAction(ISD::CTPOP, MVT::i32, Promote);
1361 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
1425 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ,
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 81 setOperationAction(ISD::CTPOP, T, Legal);
146 setOperationAction(ISD::CTPOP, T, Custom);
1532 case ISD::CTPOP:
lib/Target/Lanai/LanaiISelLowering.cpp 126 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
lib/Target/MSP430/MSP430ISelLowering.cpp 104 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
105 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
lib/Target/Mips/MipsISelLowering.cpp 417 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
418 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
420 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
421 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
lib/Target/Mips/MipsSEISelLowering.cpp 335 setOperationAction(ISD::CTPOP, Ty, Legal);
2118 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
lib/Target/NVPTX/NVPTXISelLowering.cpp 501 setOperationAction(ISD::CTPOP, Ty, Legal);
lib/Target/PowerPC/PPCISelLowering.cpp 340 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
341 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
343 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
344 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
588 setOperationAction(ISD::CTPOP, VT, Legal);
592 setOperationAction(ISD::CTPOP, VT, Expand);
lib/Target/RISCV/RISCVISelLowering.cpp 141 setOperationAction(ISD::CTPOP, XLenVT, Expand);
lib/Target/Sparc/SparcISelLowering.cpp 1565 setOperationAction(ISD::CTPOP, MVT::i64,
1699 setOperationAction(ISD::CTPOP, MVT::i32,
lib/Target/SystemZ/SystemZISelLowering.cpp 189 setOperationAction(ISD::CTPOP, VT, Custom);
191 setOperationAction(ISD::CTPOP, VT, Expand);
263 setOperationAction(ISD::CTPOP, MVT::i32, Promote);
264 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
349 setOperationAction(ISD::CTPOP, VT, Legal);
351 setOperationAction(ISD::CTPOP, VT, Custom);
4976 case ISD::CTPOP:
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 175 for (auto Op : {ISD::CTLZ, ISD::CTTZ, ISD::CTPOP, ISD::SDIV, ISD::UDIV,
lib/Target/X86/X86ISelLowering.cpp 396 setOperationPromotedToType(ISD::CTPOP, MVT::i8, MVT::i32);
398 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
399 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
400 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
402 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
404 setOperationAction(ISD::CTPOP , MVT::i64 , Custom);
767 setOperationAction(ISD::CTPOP, VT, Expand);
898 setOperationAction(ISD::CTPOP, VT, Custom);
1172 setOperationAction(ISD::CTPOP, VT, Custom);
1458 setOperationAction(ISD::CTPOP, VT, Custom);
1488 setOperationAction(ISD::CTPOP, VT, Legal);
1583 setOperationAction(ISD::CTPOP, VT, Legal);
1676 setOperationAction(ISD::CTPOP, VT, Custom);
1701 setOperationAction(ISD::CTPOP, VT, Legal);
1722 setOperationAction(ISD::CTPOP, VT, Legal);
26965 Op = DAG.getNode(ISD::CTPOP, DL, NewVT, Op);
26982 SDValue PopCnt8 = DAG.getNode(ISD::CTPOP, DL, ByteVT, ByteOp);
27666 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
27828 case ISD::CTPOP: {
27837 Wide = DAG.getNode(ISD::CTPOP, dl, MVT::v2i64, Wide);
35924 SDValue Result = DAG.getNode(ISD::CTPOP, DL, CmpVT, Movmsk);
39049 if (TLI.isTypeLegal(VT) && TLI.isOperationLegal(ISD::CTPOP, VT))
39056 if (N0.getOpcode() != ISD::CTPOP || !N0.hasOneUse())
39077 DAG.getNode(ISD::CTPOP, DL, MVT::i32, X),
lib/Target/X86/X86TargetTransformInfo.cpp 1909 { ISD::CTPOP, MVT::v8i64, 7 },
1910 { ISD::CTPOP, MVT::v16i32, 11 },
1911 { ISD::CTPOP, MVT::v32i16, 9 },
1912 { ISD::CTPOP, MVT::v64i8, 6 },
1931 { ISD::CTPOP, MVT::v8i64, 16 },
1932 { ISD::CTPOP, MVT::v16i32, 24 },
1970 { ISD::CTPOP, MVT::v4i64, 7 },
1971 { ISD::CTPOP, MVT::v8i32, 11 },
1972 { ISD::CTPOP, MVT::v16i16, 9 },
1973 { ISD::CTPOP, MVT::v32i8, 6 },
2007 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert
2008 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert
2009 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert
2010 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert
2062 { ISD::CTPOP, MVT::v2i64, 7 },
2063 { ISD::CTPOP, MVT::v4i32, 11 },
2064 { ISD::CTPOP, MVT::v8i16, 9 },
2065 { ISD::CTPOP, MVT::v16i8, 6 },
2083 { ISD::CTPOP, MVT::v2i64, 12 },
2084 { ISD::CTPOP, MVT::v4i32, 15 },
2085 { ISD::CTPOP, MVT::v8i16, 13 },
2086 { ISD::CTPOP, MVT::v16i8, 10 },
2115 { ISD::CTPOP, MVT::i64, 1 },
2118 { ISD::CTPOP, MVT::i32, 1 },
2119 { ISD::CTPOP, MVT::i16, 1 },
2120 { ISD::CTPOP, MVT::i8, 1 },
2125 { ISD::CTPOP, MVT::i64, 10 },
2136 { ISD::CTPOP, MVT::i32, 8 },
2137 { ISD::CTPOP, MVT::i16, 9 },
2138 { ISD::CTPOP, MVT::i8, 7 },
2162 ISD = ISD::CTPOP;
lib/Target/XCore/XCoreISelLowering.cpp 106 setOperationAction(ISD::CTPOP, MVT::i32, Expand);