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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenRegisterBank.inc 134 assert(Index++ == RB->getID() && "Index != ID");
gen/lib/Target/AMDGPU/AMDGPUGenRegisterBank.inc 233 assert(Index++ == RB->getID() && "Index != ID");
gen/lib/Target/ARM/ARMGenRegisterBank.inc 109 assert(Index++ == RB->getID() && "Index != ID");
gen/lib/Target/Mips/MipsGenRegisterBank.inc 98 assert(Index++ == RB->getID() && "Index != ID");
gen/lib/Target/RISCV/RISCVGenRegisterBank.inc 61 assert(Index++ == RB->getID() && "Index != ID");
gen/lib/Target/X86/X86GenRegisterBank.inc 152 assert(Index++ == RB->getID() && "Index != ID");
lib/CodeGen/GlobalISel/RegisterBank.cpp 75 assert((OtherRB.getID() != getID() || &OtherRB == this) &&
75 assert((OtherRB.getID() != getID() || &OtherRB == this) &&
91 OS << "(ID:" << getID() << ", Size:" << getSize() << ")\n"
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp 73 assert(Idx == RegBank.getID() &&
263 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0);
lib/Target/AArch64/AArch64InstructionSelector.cpp 307 if (RB.getID() == AArch64::GPRRegBankID) {
317 if (RB.getID() == AArch64::FPRRegBankID) {
337 unsigned RegBankID = RB.getID();
577 assert((DstSize <= 64 || DstBank.getID() == AArch64::FPRRegBankID) &&
718 if (DstRegBank.getID() != SrcRegBank.getID()) {
718 if (DstRegBank.getID() != SrcRegBank.getID()) {
719 if (DstRegBank.getID() == AArch64::GPRRegBankID && DstSize == 32 &&
834 bool IsFP = (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() !=
984 if (RB.getID() != AArch64::GPRRegBankID)
1508 if (RB.getID() != AArch64::FPRRegBankID) {
1528 if (RB.getID() != AArch64::GPRRegBankID) {
1598 assert(SrcRB.getID() == AArch64::FPRRegBankID &&
1599 DstRB.getID() == AArch64::FPRRegBankID &&
1748 assert(PtrRB.getID() == AArch64::GPRRegBankID &&
1758 selectLoadStoreUIOp(I.getOpcode(), RB.getID(), MemSizeInBits);
1830 if (RB.getID() != AArch64::GPRRegBankID) {
1874 const unsigned NewOpc = selectBinaryOp(I.getOpcode(), RB.getID(), OpSize);
1952 if (DstRB.getID() != SrcRB.getID()) {
1952 if (DstRB.getID() != SrcRB.getID()) {
1958 if (DstRB.getID() == AArch64::GPRRegBankID) {
1992 } else if (DstRB.getID() == AArch64::FPRRegBankID) {
2018 if (RBDst.getID() != AArch64::GPRRegBankID) {
2025 if (RBSrc.getID() != AArch64::GPRRegBankID) {
2071 assert((*RBI.getRegBank(DefReg, MRI, TRI)).getID() ==
2087 RBI.getRegBank(SrcReg, MRI, TRI)->getID() == AArch64::GPRRegBankID) {
2743 if (RB.getID() != AArch64::GPRRegBankID)
2881 if (RBI.getRegBank(DstReg, MRI, TRI)->getID() != AArch64::FPRRegBankID) {
2940 if (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() !=
2942 RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI)->getID() !=
3114 if (RB.getID() == AArch64::GPRRegBankID) {
3617 bool IsFP = ScalarRB->getID() == AArch64::FPRRegBankID;
3757 if (RB.getID() == AArch64::FPRRegBankID) {
3983 if (RBI.getRegBank(SrcReg, MRI, TRI)->getID() != AArch64::FPRRegBankID) {
3992 if (RBI.getRegBank(DstReg, MRI, TRI)->getID() != AArch64::FPRRegBankID)
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 585 getCopyMapping(DstRB->getID(), SrcRB->getID(), Size),
585 getCopyMapping(DstRB->getID(), SrcRB->getID(), Size),
604 getCopyMapping(DstRB.getID(), SrcRB.getID(), Size),
604 getCopyMapping(DstRB.getID(), SrcRB.getID(), Size),
lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def 153 assert(BankID == ValMappings[Idx].BreakDown->RegBank->getID());
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 91 return RB->getID() == AMDGPU::SCCRegBankID;
109 return RB->getID() == AMDGPU::VCCRegBankID;
198 if (RB.getID() == AMDGPU::SCCRegBankID) {
270 if (DstRB->getID() == AMDGPU::VCCRegBankID) {
290 if (DstRB->getID() == AMDGPU::SGPRRegBankID) {
306 const bool IsSALU = DstRB->getID() == AMDGPU::SGPRRegBankID;
1234 if (SrcBank->getID() == AMDGPU::SCCRegBankID) {
1259 if (SrcBank->getID() == AMDGPU::VCCRegBankID && DstSize <= 32) {
1277 if (SrcBank->getID() == AMDGPU::VGPRRegBankID && DstSize <= 32) {
1301 if (SrcBank->getID() == AMDGPU::SGPRRegBankID && DstSize <= 64) {
1415 IsSgpr = RB->getID() == AMDGPU::SGPRRegBankID;
1498 if (OpBank->getID() == AMDGPU::SGPRRegBankID)
1603 const bool IsVGPR = DstRB->getID() == AMDGPU::VGPRRegBankID;
1623 const bool IsVGPR = DstRB->getID() == AMDGPU::VGPRRegBankID;
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 115 if (Dst.getID() == AMDGPU::SGPRRegBankID &&
116 Src.getID() == AMDGPU::VGPRRegBankID) {
128 (Dst.getID() == AMDGPU::SCCRegBankID ||
129 Dst.getID() == AMDGPU::SGPRRegBankID) &&
130 (Src.getID() == AMDGPU::SGPRRegBankID ||
131 Src.getID() == AMDGPU::VGPRRegBankID ||
132 Src.getID() == AMDGPU::VCCRegBankID))
135 if (Dst.getID() == AMDGPU::SCCRegBankID &&
136 Src.getID() == AMDGPU::VCCRegBankID)
968 if (OpBank->getID() == AMDGPU::VGPRRegBankID)
1546 SrcBank->getID() == AMDGPU::SCCRegBankID;
1557 if (DstSize > 32 && SrcBank->getID() != AMDGPU::SCCRegBankID) {
1911 if (Bank->getID() == AMDGPU::VGPRRegBankID)
1914 assert(Bank->getID() == AMDGPU::SGPRRegBankID ||
1915 Bank->getID() == AMDGPU::SCCRegBankID);
2077 return Bank ? Bank->getID() : Default;
2151 if (!Bank || Bank->getID() == AMDGPU::VGPRRegBankID) {
2156 unsigned OpBank = Bank->getID();
2206 TargetBankID = DstBank->getID();
2434 switch (SrcBank->getID()) {
2447 OpdsMapping[1] = AMDGPU::getValueMapping(SrcBank->getID(), SrcSize);
2452 OpdsMapping[1] = AMDGPU::getValueMappingSGPR64Only(SrcBank->getID(),
lib/Target/AMDGPU/SIRegisterInfo.cpp 1781 switch (RB.getID()) {
1802 return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VGPR_32RegClass :
1805 return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_64RegClass :
1808 return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_96RegClass :
1811 return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_128RegClass :
1814 return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_160RegClass :
1817 return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_256RegClass :
1820 return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_512RegClass :
1823 return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_1024RegClass :
1827 return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VGPR_32RegClass :
lib/Target/ARM/ARMInstructionSelector.cpp 192 assert((RegBank->getID() == ARM::GPRRegBankID ||
193 RegBank->getID() == ARM::FPRRegBankID) &&
196 if (RegBank->getID() == ARM::FPRRegBankID) {
242 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID &&
247 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
252 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID &&
274 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID &&
279 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
284 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID &&
517 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) {
920 if (SrcRegBank.getID() == ARM::FPRRegBankID) {
925 assert(DstRegBank.getID() == ARM::GPRRegBankID &&
945 if (SrcRegBank.getID() != DstRegBank.getID()) {
945 if (SrcRegBank.getID() != DstRegBank.getID()) {
951 if (SrcRegBank.getID() != ARM::GPRRegBankID) {
1015 if (SrcRegBank.getID() != DstRegBank.getID()) {
1015 if (SrcRegBank.getID() != DstRegBank.getID()) {
1022 if (SrcRegBank.getID() != ARM::GPRRegBankID) {
1085 unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID();
lib/Target/ARM/ARMRegisterBankInfo.cpp 52 PM.RegBank->getID() == RegBankID;
474 (Mapping.RegBank->getID() != ARM::FPRRegBankID ||
lib/Target/Mips/MipsInstructionSelector.cpp 97 if (RegBank->getID() == Mips::FPRBRegBankID) {
116 if (RB.getID() == Mips::GPRBRegBankID)
119 if (RB.getID() == Mips::FPRBRegBankID)
169 const unsigned RegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID();
243 (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() ==
lib/Target/X86/X86InstructionSelector.cpp 169 if (RB.getID() == X86::GPRRegBankID) {
179 if (RB.getID() == X86::VECRRegBankID) {
243 if (DstSize > SrcSize && SrcRegBank.getID() == X86::GPRRegBankID &&
244 DstRegBank.getID() == X86::GPRRegBankID) {
279 if (SrcRegBank.getID() == X86::GPRRegBankID &&
280 DstRegBank.getID() == X86::GPRRegBankID && SrcSize > DstSize &&
403 if (X86::GPRRegBankID == RB.getID())
406 if (X86::GPRRegBankID == RB.getID())
409 if (X86::GPRRegBankID == RB.getID())
411 if (X86::VECRRegBankID == RB.getID())
419 if (X86::GPRRegBankID == RB.getID())
421 if (X86::VECRRegBankID == RB.getID())
641 if (RBI.getRegBank(DefReg, MRI, TRI)->getID() != X86::GPRRegBankID)
720 if (DstRB.getID() != SrcRB.getID()) {
720 if (DstRB.getID() != SrcRB.getID()) {
738 if (DstRB.getID() != X86::GPRRegBankID)
895 assert(DstRB.getID() == SrcRB.getID() &&
895 assert(DstRB.getID() == SrcRB.getID() &&
910 if (DstRB.getID() != X86::GPRRegBankID)
1535 if (!RegRB || RegRB->getID() != X86::GPRRegBankID)