1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
| //===- AMDGPUGenRegisterBankInfo.def -----------------------------*- C++ -*-==//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
/// \file
/// This file defines all the static objects used by AMDGPURegisterBankInfo.
/// \todo This should be generated by TableGen.
//===----------------------------------------------------------------------===//
namespace llvm {
namespace AMDGPU {
enum PartialMappingIdx {
None = - 1,
PM_SGPR1 = 2,
PM_SGPR16 = 6,
PM_SGPR32 = 7,
PM_SGPR64 = 8,
PM_SGPR128 = 9,
PM_SGPR256 = 10,
PM_SGPR512 = 11,
PM_SGPR1024 = 12,
PM_VGPR1 = 13,
PM_VGPR16 = 17,
PM_VGPR32 = 18,
PM_VGPR64 = 19,
PM_VGPR128 = 20,
PM_VGPR256 = 21,
PM_VGPR512 = 22,
PM_VGPR1024 = 23,
PM_SGPR96 = 24,
PM_VGPR96 = 25
};
const RegisterBankInfo::PartialMapping PartMappings[] {
// StartIdx, Length, RegBank
{0, 1, SCCRegBank},
{0, 1, VCCRegBank},
{0, 1, SGPRRegBank}, // SGPR begin
{0, 16, SGPRRegBank},
{0, 32, SGPRRegBank},
{0, 64, SGPRRegBank},
{0, 128, SGPRRegBank},
{0, 256, SGPRRegBank},
{0, 512, SGPRRegBank},
{0, 1024, SGPRRegBank},
{0, 1, VGPRRegBank}, // VGPR begin
{0, 16, VGPRRegBank},
{0, 32, VGPRRegBank},
{0, 64, VGPRRegBank},
{0, 128, VGPRRegBank},
{0, 256, VGPRRegBank},
{0, 512, VGPRRegBank},
{0, 1024, VGPRRegBank},
{0, 96, SGPRRegBank},
{0, 96, VGPRRegBank}
};
const RegisterBankInfo::ValueMapping ValMappings[] {
// SCC
{&PartMappings[0], 1},
// VCC
{&PartMappings[1], 1},
// SGPRs
{&PartMappings[2], 1}, // 1
{nullptr, 0}, // Illegal power of 2 sizes
{nullptr, 0},
{nullptr, 0},
{&PartMappings[3], 1}, // 16
{&PartMappings[4], 1}, // 32
{&PartMappings[5], 1}, // 64
{&PartMappings[6], 1}, // 128
{&PartMappings[7], 1}, // 256
{&PartMappings[8], 1}, // 512
{&PartMappings[9], 1}, // 1024
// VGPRs
{&PartMappings[10], 1}, // 1
{nullptr, 0},
{nullptr, 0},
{nullptr, 0},
{&PartMappings[11], 1}, // 16
{&PartMappings[12], 1}, // 32
{&PartMappings[13], 1}, // 64
{&PartMappings[14], 1}, // 128
{&PartMappings[15], 1}, // 256
{&PartMappings[16], 1}, // 512
{&PartMappings[17], 1}, // 1024
{&PartMappings[18], 1},
{&PartMappings[19], 1}
};
const RegisterBankInfo::PartialMapping SGPROnly64BreakDown[] {
{0, 32, SGPRRegBank}, // 32-bit op
{0, 32, SGPRRegBank}, // 2x32-bit op
{32, 32, SGPRRegBank},
{0, 64, SGPRRegBank}, // <2x32-bit> op
{0, 32, VGPRRegBank}, // 32-bit op
{0, 32, VGPRRegBank}, // 2x32-bit op
{32, 32, VGPRRegBank},
};
// For some instructions which can operate 64-bit only for the scalar version.
const RegisterBankInfo::ValueMapping ValMappingsSGPR64OnlyVGPR32[] {
/*32-bit sgpr*/ {&SGPROnly64BreakDown[0], 1},
/*2 x 32-bit sgpr*/ {&SGPROnly64BreakDown[1], 2},
/*64-bit sgpr */ {&SGPROnly64BreakDown[3], 1},
/*32-bit vgpr*/ {&SGPROnly64BreakDown[4], 1},
/*2 x 32-bit vgpr*/ {&SGPROnly64BreakDown[5], 2}
};
enum ValueMappingIdx {
SCCStartIdx = 0,
SGPRStartIdx = 2,
VGPRStartIdx = 13
};
const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
unsigned Size) {
unsigned Idx;
switch (Size) {
case 1:
if (BankID == AMDGPU::SCCRegBankID)
return &ValMappings[0];
if (BankID == AMDGPU::VCCRegBankID)
return &ValMappings[1];
// 1-bit values not from a compare etc.
Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR1 : PM_VGPR1;
break;
case 96:
assert(BankID != AMDGPU::VCCRegBankID);
Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR96 : PM_VGPR96;
break;
default:
assert(BankID != AMDGPU::VCCRegBankID);
Idx = BankID == AMDGPU::VGPRRegBankID ? VGPRStartIdx : SGPRStartIdx;
Idx += Log2_32_Ceil(Size);
break;
}
assert(Log2_32_Ceil(Size) == Log2_32_Ceil(ValMappings[Idx].BreakDown->Length));
assert(BankID == ValMappings[Idx].BreakDown->RegBank->getID());
return &ValMappings[Idx];
}
const RegisterBankInfo::ValueMapping *getValueMappingSGPR64Only(unsigned BankID,
unsigned Size) {
if (Size != 64)
return getValueMapping(BankID, Size);
if (BankID == AMDGPU::VGPRRegBankID)
return &ValMappingsSGPR64OnlyVGPR32[4];
assert(BankID == AMDGPU::SGPRRegBankID);
return &ValMappingsSGPR64OnlyVGPR32[2];
}
const RegisterBankInfo::PartialMapping LoadSGPROnlyBreakDown[] {
/* 256-bit load */ {0, 256, SGPRRegBank},
/* 512-bit load */ {0, 512, SGPRRegBank},
/* 8 32-bit loads */ {0, 32, VGPRRegBank}, {32, 32, VGPRRegBank},
{64, 32, VGPRRegBank}, {96, 32, VGPRRegBank},
{128, 32, VGPRRegBank}, {160, 32, VGPRRegBank},
{192, 32, VGPRRegBank}, {224, 32, VGPRRegBank},
/* 16 32-bit loads */ {0, 32, VGPRRegBank}, {32, 32, VGPRRegBank},
{64, 32, VGPRRegBank}, {96, 32, VGPRRegBank},
{128, 32, VGPRRegBank}, {160, 32, VGPRRegBank},
{192, 32, VGPRRegBank}, {224, 32, VGPRRegBank},
{256, 32, VGPRRegBank}, {288, 32, VGPRRegBank},
{320, 32, VGPRRegBank}, {352, 32, VGPRRegBank},
{384, 32, VGPRRegBank}, {416, 32, VGPRRegBank},
{448, 32, VGPRRegBank}, {480, 32, VGPRRegBank},
/* 4 64-bit loads */ {0, 64, VGPRRegBank}, {64, 64, VGPRRegBank},
{128, 64, VGPRRegBank}, {192, 64, VGPRRegBank},
/* 8 64-bit loads */ {0, 64, VGPRRegBank}, {64, 64, VGPRRegBank},
{128, 64, VGPRRegBank}, {192, 64, VGPRRegBank},
{256, 64, VGPRRegBank}, {320, 64, VGPRRegBank},
{384, 64, VGPRRegBank}, {448, 64, VGPRRegBank},
/* FIXME: The generic register bank select does not support complex
* break downs where the number of vector elements does not equal the
* number of breakdowns.
* FIXME: register bank select now tries to handle complex break downs,
* but it emits an illegal instruction:
* %1:vgpr(<8 x s32>) = G_CONCAT_VECTORS %2:vgpr(s128), %3:vgpr(s128)
*/
/* 2 128-bit loads */ {0, 128, VGPRRegBank}, {128, 128, VGPRRegBank},
/* 4 128-bit loads */ {0, 128, VGPRRegBank}, {128, 128, VGPRRegBank},
{256, 128, VGPRRegBank}, {384, 128, VGPRRegBank}
};
const RegisterBankInfo::ValueMapping ValMappingsLoadSGPROnly[] {
/* 256-bit load */ {&LoadSGPROnlyBreakDown[0], 1},
/* 512-bit load */ {&LoadSGPROnlyBreakDown[1], 1},
/* <8 x i32> load */ {&LoadSGPROnlyBreakDown[2], 8},
/* <16 x i32> load */ {&LoadSGPROnlyBreakDown[10], 16},
/* <4 x i64> load */ {&LoadSGPROnlyBreakDown[26], 4},
/* <8 x i64> load */ {&LoadSGPROnlyBreakDown[30], 8}
};
const RegisterBankInfo::ValueMapping *
getValueMappingLoadSGPROnly(unsigned BankID, LLT SizeTy) {
unsigned Size = SizeTy.getSizeInBits();
if (Size < 256 || BankID == AMDGPU::SGPRRegBankID)
return getValueMapping(BankID, Size);
assert((Size == 256 || Size == 512) && BankID == AMDGPU::VGPRRegBankID);
// Default to using the non-split ValueMappings, we will use these if
// the register bank is SGPR or if we don't know how to handle the vector
// type.
unsigned Idx = Size == 256 ? 0 : 1;
// We need to split this load if it has a vgpr pointer.
if (BankID == AMDGPU::VGPRRegBankID) {
if (SizeTy == LLT::vector(8, 32))
Idx = 2;
else if (SizeTy == LLT::vector(16, 32))
Idx = 3;
else if (SizeTy == LLT::vector(4, 64))
Idx = 4;
else if (SizeTy == LLT::vector(8, 64))
Idx = 5;
}
return &ValMappingsLoadSGPROnly[Idx];
}
} // End AMDGPU namespace.
} // End llvm namespace.
|