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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc 4575 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
9174 case ARM::CPSR: OpKind = MCK_CCR; break;
gen/lib/Target/ARM/ARMGenDAGISel.inc 907 /* 1844*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
921 /* 1877*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
1071 /* 2242*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
1080 /* 2266*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
1172 /* 2483*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
5193 /* 10518*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
5206 /* 10548*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
5219 /* 10578*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
5233 /* 10611*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
5330 /* 10851*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
5800 /* 11867*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
9356 /* 19764*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
9393 /* 19857*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
9558 /* 20226*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
21755 /* 46732*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
21781 /* 46795*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
27686 /* 59812*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
27687 /* 59815*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
27708 /* 59882*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
27709 /* 59885*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
27734 /* 59960*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
27735 /* 59963*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
27756 /* 60030*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
27757 /* 60033*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
30883 /* 67975*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
30936 /* 68096*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
31811 /* 69965*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
32914 /* 72445*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
33010 /* 72656*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
33036 /* 72719*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
33227 /* 73125*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
33352 /* 73400*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
34762 /* 76566*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
34772 /* 76596*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
34784 /* 76628*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
34804 /* 76675*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
34819 /* 76710*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
34835 /* 76748*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
34850 /* 76783*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
34866 /* 76821*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
34887 /* 76876*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
34903 /* 76923*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
34918 /* 76957*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
34925 /* 76975*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
34935 /* 76999*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
34956 /* 77049*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
34966 /* 77079*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
34976 /* 77109*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
34986 /* 77138*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
34998 /* 77170*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
35016 /* 77211*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
35035 /* 77252*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
35054 /* 77294*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
35067 /* 77326*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
35074 /* 77344*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
35084 /* 77368*/ OPC_EmitCopyToReg, 2, ARM::CPSR,
35411 /* 78078*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
35425 /* 78110*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
37587 /* 82796*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
37620 /* 82873*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
37621 /* 82876*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
37639 /* 82927*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
37640 /* 82930*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
37656 /* 82975*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
37657 /* 82978*/ OPC_EmitRegister, MVT::i32, ARM::CPSR,
gen/lib/Target/ARM/ARMGenInstrInfo.inc 5296 static const MCPhysReg ImplicitList1[] = { ARM::CPSR, 0 };
5300 static const MCPhysReg ImplicitList5[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 0 };
5301 static const MCPhysReg ImplicitList6[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, 0 };
5302 static const MCPhysReg ImplicitList7[] = { ARM::R0, ARM::R12, ARM::LR, ARM::CPSR, 0 };
5310 static const MCPhysReg ImplicitList15[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 0 };
5312 static const MCPhysReg ImplicitList17[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::CPSR, 0 };
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 1481 { ARM::CPSR },
1857 ARM::CPSR,
lib/Target/ARM/ARMAsmPrinter.cpp 1674 .addReg(ARM::CPSR)
1730 .addReg(ARM::CPSR)
1861 .addReg(ARM::CPSR)
1880 .addReg(ARM::CPSR)
1895 .addReg(ARM::CPSR)
lib/Target/ARM/ARMBaseInstrInfo.cpp 550 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
551 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
562 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
687 if (MO.getReg() != ARM::CPSR)
785 .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
805 .addReg(ARM::CPSR, RegState::Implicit | RegState::Define);
923 } else if (SrcReg == ARM::CPSR) {
926 } else if (DestReg == ARM::CPSR) {
2159 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
2978 if (I != E && !MI->readsRegister(ARM::CPSR, TRI)) {
3013 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
3014 Instr.readsRegister(ARM::CPSR, TRI))
3059 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
3063 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
3159 if ((*SI)->isLiveIn(ARM::CPSR))
3166 MI->getOperand(5).setReg(ARM::CPSR);
3178 MI->clearRegisterDeads(ARM::CPSR);
3219 if (MO.getReg() == ARM::CPSR && !MO.isDead())
3228 if (UseMI.getOperand(NumOps - 1).getReg() == ARM::CPSR)
4294 if (Reg == ARM::CPSR) {
4616 if (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) &&
4646 if (PredCost && (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) &&
5371 if (CmpMI->modifiesRegister(ARM::CPSR, TRI))
5373 if (CmpMI->readsRegister(ARM::CPSR, TRI))
lib/Target/ARM/ARMBaseInstrInfo.h 479 return MachineOperand::CreateReg(ARM::CPSR,
lib/Target/ARM/ARMConstantIslandPass.cpp 1868 if (!Br.MI->killsRegister(ARM::CPSR))
lib/Target/ARM/ARMExpandPseudoInsts.cpp 983 .addReg(ARM::CPSR, RegState::Kill);
1006 .addReg(ARM::CPSR, RegState::Kill);
1098 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
1104 .addReg(ARM::CPSR, RegState::Kill);
1126 .addReg(ARM::CPSR, RegState::Kill);
1390 .addReg(ARM::CPSR, RegState::Define);
1581 .addReg(ARM::CPSR, RegState::Undef);
lib/Target/ARM/ARMFastISel.cpp 257 if (MO.getReg() == ARM::CPSR)
1267 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1290 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1328 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1493 .addImm(ARMPred).addReg(ARM::CPSR);
1677 .addReg(ARM::CPSR);
1685 .addReg(ARM::CPSR);
2724 MIB.addReg(ARM::CPSR, RegState::Define);
lib/Target/ARM/ARMFrameLowering.cpp 2459 .addReg(ARM::CPSR);
lib/Target/ARM/ARMISelDAGToDAG.cpp 107 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
2884 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), Src,
3140 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32),
3421 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), X,
lib/Target/ARM/ARMISelLowering.cpp 4283 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
4437 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4557 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5009 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5044 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5151 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5200 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5254 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5263 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5280 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5799 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5843 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
6359 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
6360 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, ARM::CPSR,
9420 .addReg(ARM::CPSR, RegState::Define)
9425 .addReg(ARM::CPSR, RegState::Define)
9608 .addReg(ARM::CPSR);
9665 .addReg(ARM::CPSR);
9669 .addReg(ARM::CPSR, RegState::Define)
9681 .addReg(ARM::CPSR, RegState::Define)
9700 .addReg(ARM::CPSR, RegState::Define)
9767 .addReg(ARM::CPSR);
10219 MIB->getOperand(5).setReg(ARM::CPSR);
10224 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
10296 .addReg(ARM::CPSR,
10312 .addReg(ARM::CPSR,
10355 .addReg(ARM::CPSR);
10373 if (mi.readsRegister(ARM::CPSR))
10375 if (mi.definesRegister(ARM::CPSR))
10386 if (succ->isLiveIn(ARM::CPSR))
10393 SelectItr->addRegisterKilled(ARM::CPSR, TRI);
10499 if (!MI.killsRegister(ARM::CPSR) &&
10501 copy0MBB->addLiveIn(ARM::CPSR);
10502 sinkMBB->addLiveIn(ARM::CPSR);
10558 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
10568 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
10577 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
10652 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
10785 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
10809 MO.setReg(ARM::CPSR);
14345 SDValue CPSRGlue = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
14359 SDValue CPSRGlue = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
15744 return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
lib/Target/ARM/ARMInstructionSelector.cpp 601 .add(predOps(Cond, ARM::CPSR));
795 .add(predOps(ARMCC::EQ, ARM::CPSR));
1152 .add(predOps(ARMCC::NE, ARM::CPSR));
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 207 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead())
635 (MBB.computeRegisterLiveness(TRI, ARM::CPSR, InsertBefore, 20) ==
lib/Target/ARM/ARMLowOverheadLoops.cpp 376 MIB.addReg(ARM::CPSR);
388 if (auto *Def = SearchForDef(MI, MBB->end(), ARM::CPSR)) {
389 if (!SearchForUse(MI, MBB->end(), ARM::CPSR) &&
404 MIB.addReg(ARM::CPSR);
437 MIB.addReg(ARM::CPSR);
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 2345 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
6860 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
9501 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
9551 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
9558 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
9604 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
9612 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
9800 Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) ||
9949 Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
9970 Inst.getOperand(4).getReg() == ARM::CPSR &&
10087 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
10123 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
10200 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
10204 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
10207 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
10237 if (Inst.getOperand(4).getReg() == ARM::CPSR &&
lib/Target/ARM/Disassembler/ARMDisassembler.cpp 737 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
742 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
838 MI.insert(CCI, MCOperand::createReg(ARM::CPSR));
900 I->setReg(ARM::CPSR);
1425 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1432 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp 998 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp 311 return MI.getOperand(Op).getReg() == ARM::CPSR;
730 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
lib/Target/ARM/Thumb1FrameLowering.cpp 417 .addDef(ARM::CPSR)
423 .addDef(ARM::CPSR)
lib/Target/ARM/Thumb1InstrInfo.cpp 59 if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I)
63 ->addRegisterDead(ARM::CPSR, RegInfo);
lib/Target/ARM/Thumb2ITBlockPass.cpp 173 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
lib/Target/ARM/Thumb2InstrInfo.cpp 486 !MI.definesRegister(ARM::CPSR)) {
lib/Target/ARM/Thumb2SizeReduction.cpp 256 if (*Regs == ARM::CPSR)
304 if (Reg == 0 || Reg == ARM::CPSR)
384 if (Reg == 0 || Reg == ARM::CPSR)
647 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)
808 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
872 if (!Reg || Reg == ARM::CPSR)
900 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
952 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
977 if (MO.getReg() != ARM::CPSR)
992 if (MO.getReg() != ARM::CPSR)
1033 bool LiveCPSR = MBB.isLiveIn(ARM::CPSR);
1088 if (BundleMI->killsRegister(ARM::CPSR))
1090 MachineOperand *MO = BundleMI->findRegisterDefOperand(ARM::CPSR);
1093 MO = BundleMI->findRegisterUseOperand(ARM::CPSR);