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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc10879 { 754 /* orr */, ARM::t2ORRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10887 { 754 /* orr */, ARM::t2ORRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
10890 { 754 /* orr */, ARM::t2ORRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10898 { 754 /* orr */, ARM::t2ORRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
gen/lib/Target/ARM/ARMGenDAGISel.inc 1184 /* 2515*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::t2ORRrr), 0,
3349 /* 6769*/ OPC_EmitNode1, TARGET_VAL(ARM::t2ORRrr), 0,
3367 /* 6826*/ OPC_EmitNode1, TARGET_VAL(ARM::t2ORRrr), 0,
3385 /* 6883*/ OPC_EmitNode1, TARGET_VAL(ARM::t2ORRrr), 0,
gen/lib/Target/ARM/ARMGenFastISel.inc 4265 return fastEmitInst_rr(ARM::t2ORRrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/ARM/ARMGenGlobalISel.inc 7170 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORRrr,
7251 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ORRrr,
7333 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ORRrr,
7395 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ORRrr,
gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc16014 case ARM::t2ORRrr:
lib/Target/ARM/ARMBaseInstrInfo.cpp 2882 case ARM::t2ORRrr:
3247 case ARM::t2ORRrr:
3298 case ARM::t2ORRrr:
3306 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
lib/Target/ARM/ARMFastISel.cpp 1764 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
lib/Target/ARM/AsmParser/ARMAsmParser.cpp10115 case ARM::t2ORRrr:
10131 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
lib/Target/ARM/Thumb2SizeReduction.cpp 110 { ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 1,0,0 },