reference, declarationdefinition
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reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenAsmMatcher.inc
10730   { 641 /* lsl */, ARM::t2LSLrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10734   { 641 /* lsl */, ARM::t2LSLrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
10737   { 641 /* lsl */, ARM::t2LSLrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10742   { 641 /* lsl */, ARM::t2LSLrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
gen/lib/Target/ARM/ARMGenDAGISel.inc
35437 /* 78142*/          OPC_MorphNodeTo1, TARGET_VAL(ARM::t2LSLrr), 0,
gen/lib/Target/ARM/ARMGenFastISel.inc
 4435     return fastEmitInst_rr(ARM::t2LSLrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/ARM/ARMGenGlobalISel.inc
25081         GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2LSLrr,
gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc
16011     case ARM::t2LSLrr:
lib/Target/ARM/ARMBaseInstrInfo.cpp
 2891   case ARM::t2LSLrr:
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 9544     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
10077   case ARM::t2LSLrr:
10092         case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
lib/Target/ARM/Thumb2SizeReduction.cpp
  101   { ARM::t2LSLrr, 0,            ARM::tLSLrr,   0,   0,   0,   1,  0,0, 1,0,1 },