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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc10278 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10287 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
10291 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10300 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
gen/lib/Target/ARM/ARMGenDAGISel.inc 9570 /* 20258*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::t2ANDrr), 0,
13295 /* 28471*/ OPC_EmitNode1, TARGET_VAL(ARM::t2ANDrr), 0,
13313 /* 28528*/ OPC_EmitNode1, TARGET_VAL(ARM::t2ANDrr), 0,
13331 /* 28585*/ OPC_EmitNode1, TARGET_VAL(ARM::t2ANDrr), 0,
gen/lib/Target/ARM/ARMGenFastISel.inc 3517 return fastEmitInst_rr(ARM::t2ANDrr, &ARM::rGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/ARM/ARMGenGlobalISel.inc 5426 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ANDrr,
5507 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ANDrr,
5589 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ANDrr,
5651 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ANDrr,
gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc16007 case ARM::t2ANDrr:
lib/Target/ARM/ARMBaseInstrInfo.cpp 2878 case ARM::t2ANDrr:
lib/Target/ARM/AsmParser/ARMAsmParser.cpp10112 case ARM::t2ANDrr:
10129 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
lib/Target/ARM/Thumb2SizeReduction.cpp 88 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0,0 },