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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc10231 { 14 /* add */, ARM::t2ADDri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, },
10252 { 14 /* add */, ARM::t2ADDri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImm }, },
10262 { 14 /* add */, ARM::t2ADDri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImm }, },
11370 { 1600 /* sub */, ARM::t2ADDri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, },
11379 { 1600 /* sub */, ARM::t2ADDri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, },
gen/lib/Target/ARM/ARMGenDAGISel.inc 939 /* 1921*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::t2ADDri), 0,
5251 /* 10655*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::t2ADDri), 0,
gen/lib/Target/ARM/ARMGenFastISel.inc 6630 return fastEmitInst_ri(ARM::t2ADDri, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
gen/lib/Target/ARM/ARMGenGlobalISel.inc 1263 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDri,
gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc16041 case ARM::t2ADDri:
lib/Target/ARM/ARMAsmPrinter.cpp 1172 case ARM::t2ADDri:
lib/Target/ARM/ARMBaseInstrInfo.cpp 2338 {ARM::t2ADDSri, ARM::t2ADDri},
2808 OI->getOpcode() == ARM::ADDri || OI->getOpcode() == ARM::t2ADDri) &&
2869 case ARM::t2ADDri:
3289 NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2ADDri : ARM::t2SUBri;
3292 NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2SUBri : ARM::t2ADDri;
lib/Target/ARM/ARMBaseRegisterInfo.cpp 635 (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri);
lib/Target/ARM/ARMFastISel.cpp 674 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
852 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
lib/Target/ARM/ARMFrameLowering.cpp 1361 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
1529 if (MI.getOpcode() == ARM::t2ADDri || MI.getOpcode() == ARM::t2ADDri12)
lib/Target/ARM/ARMISelDAGToDAG.cpp 3046 ARM::t2ADDri : ARM::ADDri);
3418 Add = CurDAG->getMachineNode(ARM::t2ADDri, dl, MVT::i32, Ops);
lib/Target/ARM/ARMInstructionSelector.cpp 319 STORE_OPCODE(ADDri, ADDri);
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 700 isThumb2 ? ARM::t2ADDri :
1190 case ARM::t2ADDri:
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 7710 case ARM::t2ADDri:
9758 Inst.setOpcode(ARM::t2ADDri);
9790 case ARM::t2ADDri:
9804 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
lib/Target/ARM/Disassembler/ARMDisassembler.cpp 594 case ARM::t2ADDri:
lib/Target/ARM/Thumb2InstrInfo.cpp 322 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
335 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
481 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
505 MI.setDesc(TII.get(ARM::t2ADDri));
lib/Target/ARM/Thumb2SizeReduction.cpp 84 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
626 if (Opc == ARM::t2ADDri) {