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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc10236 { 14 /* add */, ARM::SUBri, Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNeg }, },
10257 { 14 /* add */, ARM::SUBri, Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNeg }, },
11356 { 1600 /* sub */, ARM::SUBri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11372 { 1600 /* sub */, ARM::SUBri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
gen/lib/Target/ARM/ARMGenDAGISel.inc 5184 /* 10499*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::SUBri), 0,
33248 /* 73172*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::SUBri), 0,
gen/lib/Target/ARM/ARMGenFastISel.inc 6328 return fastEmitInst_ri(ARM::SUBri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
gen/lib/Target/ARM/ARMGenGlobalISel.inc 3570 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SUBri,
gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc14322 case ARM::SUBri: {
lib/Target/ARM/ARMAsmPrinter.cpp 1175 case ARM::SUBri:
lib/Target/ARM/ARMBaseInstrInfo.cpp 191 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
222 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
2317 {ARM::SUBSri, ARM::SUBri},
2387 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
2544 MI.setDesc(TII.get(ARM::SUBri));
2791 (OI->getOpcode() == ARM::SUBri || OI->getOpcode() == ARM::t2SUBri) &&
2864 case ARM::SUBri:
3109 Opc == ARM::SUBri || Opc == ARM::t2SUBri ||
3260 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri;
3263 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri;
lib/Target/ARM/ARMExpandPseudoInsts.cpp 1576 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
lib/Target/ARM/ARMFrameLowering.cpp 1208 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri;
2400 BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1)
lib/Target/ARM/ARMISelLowering.cpp10214 TII->get(IsThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 710 isThumb1 ? ARM::tSUBi8 : ARM::SUBri;
1189 case ARM::SUBri: Scale = -1; CheckCPSRDef = true; break;
lib/Target/ARM/ARMMCInstLower.cpp 142 case ARM::SUBri: