reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenAsmMatcher.inc

10610   { 544 /* ldr */, ARM::LDRi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset }, },

gen/lib/Target/ARM/ARMGenDAGISel.inc

27128 /* 58546*/        OPC_MorphNodeTo1, TARGET_VAL(ARM::LDRi12), 0|OPFL_Chain|OPFL_MemRefs,
32368 /* 71235*/      OPC_MorphNodeTo1, TARGET_VAL(ARM::LDRi12), 0|OPFL_Chain|OPFL_MemRefs,

gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc

14035     case ARM::LDRi12:

lib/Target/ARM/ARMAsmPrinter.cpp

 1768     TmpInst.setOpcode(ARM::LDRi12);
 1972     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
 1980     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
 1990       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
 2000       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
 2007       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)

lib/Target/ARM/ARMBaseInstrInfo.cpp

 1295       BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
 1455   case ARM::LDRi12:
 1850   case ARM::LDRi12:
 1871   case ARM::LDRi12:

lib/Target/ARM/ARMBaseRegisterInfo.cpp

  565   case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:

lib/Target/ARM/ARMConstantIslandPass.cpp

  808           case ARM::LDRi12:

lib/Target/ARM/ARMExpandPseudoInsts.cpp

 1421                       TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg)
 1481       unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;

lib/Target/ARM/ARMFastISel.cpp

  632                     TII.get(ARM::LDRi12), NewDestReg)
  967         Opc = ARM::LDRi12;
  977         Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
 2493     unsigned LdrOpc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;

lib/Target/ARM/ARMFrameLowering.cpp

 2441     BuildMI(GetMBB, DL, TII.get(ARM::LDRi12), ScratchReg0)

lib/Target/ARM/ARMISelLowering.cpp

 9445     BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
 9711     BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)

lib/Target/ARM/ARMInstrInfo.cpp

   59     return ARM::LDRi12;
   99       expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_pcrel, ARM::LDRi12);
  101       expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_abs, ARM::LDRi12);
  106     expandLoadStackGuardBase(MI, ARM::MOVi32imm, ARM::LDRi12);
  114     expandLoadStackGuardBase(MI, ARM::MOV_ga_pcrel, ARM::LDRi12);
  131   BuildMI(MBB, MI, DL, get(ARM::LDRi12), Reg)

lib/Target/ARM/ARMInstructionSelector.cpp

  309   STORE_OPCODE(LOAD32, LDRi12);
  331   ConstPoolLoad = isThumb ? ARM::t2LDRpci : ARM::LDRi12;
  632     assert((MIB->getOpcode() == ARM::LDRi12 ||
  647     if (MIB->getOpcode() == ARM::LDRi12)

lib/Target/ARM/ARMLoadStoreOptimizer.cpp

  225       Opcode == ARM::LDRi12   || Opcode == ARM::STRi12)
  255   case ARM::LDRi12:
  400   return Opc == ARM::LDRi12 || isT1i32Load(Opc) || isT2i32Load(Opc) ;
  439   case ARM::LDRi12:
 1336   case ARM::LDRi12:
 1361   case ARM::LDRi12:
 1396   bool isAM2 = (Opcode == ARM::LDRi12 || Opcode == ARM::STRi12);
 1572   case ARM::LDRi12:
 1719       ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12)
 1724       ? (isT2 ? (OffImm+4 < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12)
 2155   if (Opcode == ARM::LDRi12) {

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

 8351       TmpInst.setOpcode(ARM::LDRi12);
 8422     if (TmpInst.getOpcode() == ARM::LDRi12)