reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc
 5066   extern const TargetRegisterClass GPR64RegClass;

References

gen/lib/Target/AArch64/AArch64GenFastISel.inc
  100   return fastEmitInst_(AArch64::MOVbaseTLS, &AArch64::GPR64RegClass);
  124   return fastEmitInst_r(AArch64::BLR, &AArch64::GPR64RegClass, Op0, Op0IsKill);
 2544   return fastEmitInst_r(AArch64::RBITXr, &AArch64::GPR64RegClass, Op0, Op0IsKill);
 2560   return fastEmitInst_r(AArch64::BR, &AArch64::GPR64RegClass, Op0, Op0IsKill);
 2581   return fastEmitInst_r(AArch64::REVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill);
 2603   return fastEmitInst_r(AArch64::CLZXr, &AArch64::GPR64RegClass, Op0, Op0IsKill);
 3263     return fastEmitInst_r(AArch64::FCVTZSUXHr, &AArch64::GPR64RegClass, Op0, Op0IsKill);
 3285     return fastEmitInst_r(AArch64::FCVTZSUXSr, &AArch64::GPR64RegClass, Op0, Op0IsKill);
 3307     return fastEmitInst_r(AArch64::FCVTZSUXDr, &AArch64::GPR64RegClass, Op0, Op0IsKill);
 3390     return fastEmitInst_r(AArch64::FCVTZUUXHr, &AArch64::GPR64RegClass, Op0, Op0IsKill);
 3412     return fastEmitInst_r(AArch64::FCVTZUUXSr, &AArch64::GPR64RegClass, Op0, Op0IsKill);
 3434     return fastEmitInst_r(AArch64::FCVTZUUXDr, &AArch64::GPR64RegClass, Op0, Op0IsKill);
 3864     return fastEmitInst_r(AArch64::FCVTASUXHr, &AArch64::GPR64RegClass, Op0, Op0IsKill);
 3872   return fastEmitInst_r(AArch64::FCVTASUXSr, &AArch64::GPR64RegClass, Op0, Op0IsKill);
 3878   return fastEmitInst_r(AArch64::FCVTASUXDr, &AArch64::GPR64RegClass, Op0, Op0IsKill);
 3901     return fastEmitInst_r(AArch64::FCVTASUXHr, &AArch64::GPR64RegClass, Op0, Op0IsKill);
 3919   return fastEmitInst_r(AArch64::FCVTASUXSr, &AArch64::GPR64RegClass, Op0, Op0IsKill);
 3935   return fastEmitInst_r(AArch64::FCVTASUXDr, &AArch64::GPR64RegClass, Op0, Op0IsKill);
 5963   return fastEmitInst_rr(AArch64::ADDXrr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 6065   return fastEmitInst_rr(AArch64::ANDXrr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 6991   return fastEmitInst_rr(AArch64::SMULHrr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 7006   return fastEmitInst_rr(AArch64::UMULHrr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 7027   return fastEmitInst_rr(AArch64::ORRXrr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 7123   return fastEmitInst_rr(AArch64::RORVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 7144   return fastEmitInst_rr(AArch64::SDIVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 7160   return fastEmitInst_rr(AArch64::LSLVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 7311   return fastEmitInst_rr(AArch64::ASRVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 7326   return fastEmitInst_rr(AArch64::LSRVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 7347   return fastEmitInst_rr(AArch64::SUBSXrr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 7449   return fastEmitInst_rr(AArch64::UDIVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 7607   return fastEmitInst_rr(AArch64::EORXrr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
 7782     return fastEmitInst_ri(AArch64::UMOVvi64, &AArch64::GPR64RegClass, Op0, Op0IsKill, imm1);
 9139   return fastEmitInst_i(AArch64::MOVi64imm, &AArch64::GPR64RegClass, imm0);
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc
 6165   &AArch64::GPR64RegClass,
 6172   &AArch64::GPR64RegClass,
 6178   &AArch64::GPR64RegClass,
 6187   &AArch64::GPR64RegClass,
 6195   &AArch64::GPR64RegClass,
 6206   &AArch64::GPR64RegClass,
 6218   &AArch64::GPR64RegClass,
 8210     &AArch64::GPR64RegClass,
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
  109     return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass);
  110   return AArch64::GPR64RegClass.contains(Reg);
lib/Target/AArch64/AArch64CallLowering.cpp
  405     unsigned X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass);
lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
  122     *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass);
lib/Target/AArch64/AArch64CollectLOH.cpp
  470       for (MCPhysReg Reg : AArch64::GPR64RegClass)
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
  750       for (unsigned ScratchReg : AArch64::GPR64RegClass) {
lib/Target/AArch64/AArch64FastISel.cpp
  388   const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass
  421         &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
  484       ResultReg = createResultReg(&AArch64::GPR64RegClass);
  497     unsigned Result64 = createResultReg(&AArch64::GPR64RegClass);
 1336       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
 1379     RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
 1423       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
 1466     RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
 1767     RC = &AArch64::GPR64RegClass;
 1869              &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;
 1874              &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;
 1879              &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;
 1883     RC = &AArch64::GPR64RegClass;
 1911     unsigned Reg64 = createResultReg(&AArch64::GPR64RegClass);
 2729     RC = &AArch64::GPR64RegClass;
 2898       DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);
 3033       RC = &AArch64::GPR64RegClass;
 3287       CallReg = createResultReg(&AArch64::GPR64RegClass);
 3480     Register SrcReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
 3491       DestReg = fastEmitInst_ri(AArch64::LDRXui, &AArch64::GPR64RegClass,
 4020       Register Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
 4054       (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
 4064   return fastEmitInst_rrr(AArch64::SMADDLrrr, &AArch64::GPR64RegClass,
 4074   return fastEmitInst_rrr(AArch64::UMADDLrrr, &AArch64::GPR64RegClass,
 4093       (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
 4121       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
 4199       (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
 4228       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
 4320       (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
 4349       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
 4462     Register Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
 4472       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
 4559     unsigned Reg64 = createResultReg(&AArch64::GPR64RegClass);
 4603         unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
 4665       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
 4864   case MVT::i64: RC = &AArch64::GPR64RegClass; break;
 4959     RC = &AArch64::GPR64RegClass;
 5106     ResRC = &AArch64::GPR64RegClass;
lib/Target/AArch64/AArch64FrameLowering.cpp
  404   for (unsigned Reg : AArch64::GPR64RegClass) {
 1855     if (AArch64::GPR64RegClass.contains(RPI.Reg1))
 1869         if (AArch64::GPR64RegClass.contains(NextReg) &&
 2207       if (AArch64::GPR64RegClass.contains(Reg) &&
 2221       if (AArch64::GPR64RegClass.contains(PairedReg) &&
 2291       const TargetRegisterClass &RC = AArch64::GPR64RegClass;
lib/Target/AArch64/AArch64ISelLowering.cpp
 3210         RC = &AArch64::GPR64RegClass;
 3339         unsigned X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass);
 3423       unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
 4256       if (AArch64::GPR64RegClass.contains(*I))
 5589   unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
12387     if (AArch64::GPR64RegClass.contains(*I))
12388       RC = &AArch64::GPR64RegClass;
lib/Target/AArch64/AArch64InstrInfo.cpp
  625   if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) {
  626     RC = &AArch64::GPR64RegClass;
 1608             AArch64::GPR64RegClass.contains(DstReg));
 2737       AArch64::GPR64RegClass.contains(SrcReg)) {
 2742   if (AArch64::GPR64RegClass.contains(DestReg) &&
 2763     assert(AArch64::GPR64RegClass.contains(SrcReg) && "Invalid NZCV copy");
 2772     assert(AArch64::GPR64RegClass.contains(DestReg) && "Invalid NZCV copy");
 2841         MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass);
 2972         MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass);
 3198       MF.getRegInfo().constrainRegClass(DstReg, &AArch64::GPR64RegClass);
 3202       MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass);
 3284           SpillRC = &AArch64::GPR64RegClass;
 4128       RC = &AArch64::GPR64RegClass;
 4143       RC = &AArch64::GPR64RegClass;
 4169       RC = &AArch64::GPR64RegClass;
 4211       RC = &AArch64::GPR64RegClass;
 4235       RC = &AArch64::GPR64RegClass;
 4261       RC = &AArch64::GPR64RegClass;
 5027   for (unsigned Reg : AArch64::GPR64RegClass) {
 5354   for (unsigned Reg : AArch64::GPR64RegClass) {
lib/Target/AArch64/AArch64InstructionSelector.cpp
  313                           : &AArch64::GPR64RegClass;
  345                           : &AArch64::GPR64RegClass;
 1093   Register ArgsAddrReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
 1122   auto MovZ = MIB.buildInstr(AArch64::MOVZXi, {&AArch64::GPR64RegClass}, {});
 1133                           : MRI.createVirtualRegister(&AArch64::GPR64RegClass);
 1303       RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI);
 1543           DefSize == 32 ? AArch64::GPR32RegClass : AArch64::GPR64RegClass;
 1982                  SrcRC == &AArch64::GPR64RegClass) {
 2104           MIB.buildInstr(AArch64::SUBREG_TO_REG, {&AArch64::GPR64RegClass}, {})
 2340   Register TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
 2394   RBI.constrainGenericRegister(I.getOperand(0).getReg(), AArch64::GPR64RegClass,
 2749   auto *DstRC = &AArch64::GPR64RegClass;
 3081       MIRBuilder.buildInstr(AArch64::ADRP, {&AArch64::GPR64RegClass}, {})
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
 1002                           LdRt, AArch64::sub_32, &AArch64::GPR64RegClass))
lib/Target/AArch64/AArch64RegisterInfo.cpp
  257     return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
  503           MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
  533       MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
tools/llvm-exegesis/lib/AArch64/Target.cpp
   49     if (AArch64::GPR64RegClass.contains(Reg))