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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc12714 { 25 /* add */, AArch64::ADDXri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR64sp, MCK_GPR64sp, MCK_AddSubImm }, },
16518 { 3356 /* mov */, AArch64::ADDXri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0, AMFBS_None, { MCK_GPR64sponly, MCK_GPR64sp }, },
16535 { 3356 /* mov */, AArch64::ADDXri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0, AMFBS_None, { MCK_GPR64sp, MCK_GPR64sponly }, },
18950 { 5924 /* sub */, AArch64::ADDXri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR64sp, MCK_GPR64sp, MCK_AddSubImmNeg }, },
20072 { 25 /* add */, AArch64::ADDXri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR64sp, MCK_GPR64sp, MCK_AddSubImm }, },
23876 { 3356 /* mov */, AArch64::ADDXri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0, AMFBS_None, { MCK_GPR64sponly, MCK_GPR64sp }, },
23893 { 3356 /* mov */, AArch64::ADDXri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0, AMFBS_None, { MCK_GPR64sp, MCK_GPR64sponly }, },
26308 { 5924 /* sub */, AArch64::ADDXri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR64sp, MCK_GPR64sp, MCK_AddSubImmNeg }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc15056 case AArch64::ADDXri:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc15772 case AArch64::ADDXri:
gen/lib/Target/AArch64/AArch64GenDAGISel.inc65513 /*159676*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::ADDXri), 0,
65519 /*159689*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::ADDXri), 0,
86920 /*200629*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::ADDXri), 0,
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc 1308 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri,
1392 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri,
4465 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ADDXri,
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc18067 case AArch64::ADDXri:
18283 case AArch64::ADDXri:
29805 case AArch64::ADDXri:
30021 case AArch64::ADDXri:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 9455 case AArch64::ADDXri:
lib/Target/AArch64/AArch64AsmPrinter.cpp 355 OutStreamer->EmitInstruction(MCInstBuilder(AArch64::ADDXri)
1043 Add.setOpcode(AArch64::ADDXri);
lib/Target/AArch64/AArch64CollectLOH.cpp 182 case AArch64::ADDXri:
313 } else if (MI.getOpcode() == AArch64::ADDXri) {
350 if (MI.getOpcode() == AArch64::ADDXri && canAddBePartOfLOH(MI)) {
528 case AArch64::ADDXri:
lib/Target/AArch64/AArch64CondBrTuning.cpp 214 case AArch64::ADDXri:
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 574 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri))
586 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri))
lib/Target/AArch64/AArch64FastISel.cpp 369 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
512 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
1057 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
1371 { AArch64::ADDWri, AArch64::ADDXri } },
3507 TII.get(AArch64::ADDXri), ResultReg)
lib/Target/AArch64/AArch64FrameLowering.cpp 191 MI.getOpcode() == AArch64::ADDXri ||
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 2967 CurDAG->SelectNodeTo(Node, AArch64::ADDXri, MVT::i64, Ops);
lib/Target/AArch64/AArch64ISelLowering.cpp 4538 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, ThreadBase,
4543 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPWithOff_lo,
4580 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, HiVar,
4583 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, LoVar,
4653 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TLS, TGAHi,
lib/Target/AArch64/AArch64InstrInfo.cpp 448 case AArch64::ADDXri:
723 case AArch64::ADDXri:
1109 return MIDefinesZeroReg ? AArch64::ADDSXri : AArch64::ADDXri;
1247 case AArch64::ADDXri:
1493 BuildMI(MBB, FirstEpilogSEH, DL, TII->get(AArch64::ADDXri))
1617 case AArch64::ADDXri: // add Xd, Xn, #0 (LSL #0)
1883 case AArch64::ADDXri:
2482 BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestRegX)
2547 BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestReg)
3054 case AArch64::ADDXri:
3149 unsigned Opc = SetNZCV ? AArch64::ADDSXri : AArch64::ADDXri;
3464 if (Opcode == AArch64::ADDSXri || Opcode == AArch64::ADDXri) {
3543 case AArch64::ADDXri:
3719 case AArch64::ADDXri:
lib/Target/AArch64/AArch64InstructionSelector.cpp 1096 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::ADDXri))
1680 I.setDesc(TII.get(AArch64::ADDXri));
3150 static const unsigned OpcTable[2][2]{{AArch64::ADDXrr, AArch64::ADDXri},
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 1376 assert((Update->getOpcode() == AArch64::ADDXri ||
1448 case AArch64::ADDXri:
lib/Target/AArch64/AArch64MacroFusion.cpp 79 case AArch64::ADDXri:
161 SecondMI.getOpcode() == AArch64::ADDXri)
lib/Target/AArch64/AArch64RegisterInfo.cpp 416 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
lib/Target/AArch64/AArch64SpeculationHardening.cpp 392 BuildMI(MBB, MBBI, DebugLoc(), TII->get(AArch64::ADDXri))
404 BuildMI(MBB, MBBI, DebugLoc(), TII->get(AArch64::ADDXri))
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 4113 case AArch64::ADDXri:
4130 Inst.getOpcode() == AArch64::ADDXri)
4144 (Inst.getOpcode() == AArch64::ADDXri ||
lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp 105 } else if (MI.getOpcode() == AArch64::ADDXri ||
109 if (MI.getOpcode() == AArch64::ADDXri)
126 MI.getOpcode() == AArch64::ADDXri ? 0x91000000: 0xF9400000;