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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
lib/Target/AMDGPU/AMDGPUInstructionSelector.h 43 class SIRegisterInfo;
lib/Target/AMDGPU/AMDGPURegisterBankInfo.h 31 class SIRegisterInfo;
lib/Target/AMDGPU/GCNHazardRecognizer.h 30 class SIRegisterInfo;
lib/Target/AMDGPU/GCNSchedStrategy.h 22 class SIRegisterInfo;
lib/Target/AMDGPU/SIFrameLowering.h 18 class SIRegisterInfo;
References
lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp 622 const SIRegisterInfo &TRI = TII->getRegisterInfo();
lib/Target/AMDGPU/AMDGPUCallLowering.cpp 328 const SIRegisterInfo *TRI = ST.getRegisterInfo();
389 const SIRegisterInfo &TRI,
444 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
569 const SIRegisterInfo *TRI = Subtarget.getRegisterInfo();
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 555 const SIRegisterInfo *TRI
1112 const SIRegisterInfo *TRI = ST->getRegisterInfo();
2047 const SIRegisterInfo *TRI = ST->getRegisterInfo();
2636 const SIRegisterInfo *SIRI =
lib/Target/AMDGPU/AMDGPUInstructionSelector.h 171 const SIRegisterInfo &TRI;
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 2114 const SIRegisterInfo *TRI
2136 const SIRegisterInfo *TRI
lib/Target/AMDGPU/AMDGPURegisterBankInfo.h 44 const SIRegisterInfo *TRI;
lib/Target/AMDGPU/AMDGPUSubtarget.h 416 const SIRegisterInfo *getRegisterInfo() const override {
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 446 const SIRegisterInfo *TRI = ST.getRegisterInfo();
468 static void addRegUnits(const SIRegisterInfo &TRI,
474 static void addRegsToSet(const SIRegisterInfo &TRI,
604 const SIRegisterInfo *TRI = ST.getRegisterInfo();
722 const SIRegisterInfo *TRI = ST.getRegisterInfo();
786 const SIRegisterInfo *TRI = ST.getRegisterInfo();
825 const SIRegisterInfo *TRI = ST.getRegisterInfo();
914 const SIRegisterInfo *TRI = ST.getRegisterInfo();
965 const SIRegisterInfo *TRI = ST.getRegisterInfo();
1037 const SIRegisterInfo *TRI = ST.getRegisterInfo();
lib/Target/AMDGPU/GCNHazardRecognizer.h 49 const SIRegisterInfo &TRI;
lib/Target/AMDGPU/GCNNSAReassign.cpp 73 const SIRegisterInfo *TRI;
lib/Target/AMDGPU/GCNRegBankReassign.cpp 141 const SIRegisterInfo *TRI;
lib/Target/AMDGPU/GCNSchedStrategy.cpp 33 const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo*>(TRI);
63 const SIRegisterInfo *SRI,
145 const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo*>(TRI);
lib/Target/AMDGPU/GCNSchedStrategy.h 40 const SIRegisterInfo *SRI,
lib/Target/AMDGPU/SIAddIMGInit.cpp 66 const SIRegisterInfo *RI = ST.getRegisterInfo();
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 117 const SIRegisterInfo *TRI;
153 const SIRegisterInfo *TRI) {
168 const SIRegisterInfo &TRI,
189 const SIRegisterInfo &TRI) {
196 const SIRegisterInfo &TRI) {
202 const SIRegisterInfo *TRI,
240 const SIRegisterInfo *TRI,
lib/Target/AMDGPU/SIFixVGPRCopies.cpp 50 const SIRegisterInfo *TRI = ST.getRegisterInfo();
lib/Target/AMDGPU/SIFixupVectorISel.cpp 89 const SIRegisterInfo *TRI) {
160 const SIRegisterInfo *TRI) {
226 const SIRegisterInfo *TRI = ST.getRegisterInfo();
lib/Target/AMDGPU/SIFoldOperands.cpp 91 const SIRegisterInfo *TRI;
1009 const SIRegisterInfo &TRI = TII->getRegisterInfo();
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 73 const SIRegisterInfo *TRI;
lib/Target/AMDGPU/SIFrameLowering.cpp 191 const SIRegisterInfo* TRI = &TII->getRegisterInfo();
272 const SIRegisterInfo *TRI,
320 const GCNSubtarget &ST, const SIInstrInfo *TII, const SIRegisterInfo *TRI,
406 const SIRegisterInfo *TRI = &TII->getRegisterInfo();
539 const SIRegisterInfo *TRI = &TII->getRegisterInfo();
694 const SIRegisterInfo &TRI = TII->getRegisterInfo();
881 const SIRegisterInfo &TRI = TII->getRegisterInfo();
945 const SIRegisterInfo *RI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
957 const SIRegisterInfo *TRI = ST.getRegisterInfo();
995 const SIRegisterInfo *TRI = ST.getRegisterInfo();
1069 const SIRegisterInfo *TRI = ST.getRegisterInfo();
lib/Target/AMDGPU/SIFrameLowering.h 65 const SIRegisterInfo *TRI,
70 const GCNSubtarget &ST, const SIInstrInfo *TII, const SIRegisterInfo *TRI,
lib/Target/AMDGPU/SIISelLowering.cpp 1615 const SIRegisterInfo &TRI,
1701 const SIRegisterInfo &TRI,
1723 const SIRegisterInfo &TRI,
1759 const SIRegisterInfo &TRI,
1865 const SIRegisterInfo &TRI,
1985 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2021 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2294 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2342 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
2444 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
2595 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2897 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
3180 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3280 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3317 computeIndirectRegAndOffset(const SIRegisterInfo &TRI,
3393 const SIRegisterInfo &TRI = TII->getRegisterInfo();
3462 static unsigned getMOVRELDPseudo(const SIRegisterInfo &TRI,
3484 const SIRegisterInfo &TRI = TII->getRegisterInfo();
3602 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3751 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3841 const SIRegisterInfo *TRI = ST.getRegisterInfo();
4551 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
10401 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
10678 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
10835 const SIRegisterInfo &TRI = ST.getInstrInfo()->getRegisterInfo();
10939 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
11017 const SIRegisterInfo *SIRI = Subtarget->getRegisterInfo();
lib/Target/AMDGPU/SIISelLowering.h 407 const SIRegisterInfo &TRI,
418 const SIRegisterInfo &TRI,
423 const SIRegisterInfo &TRI,
428 const SIRegisterInfo &TRI,
lib/Target/AMDGPU/SIInsertSkips.cpp 52 const SIRegisterInfo *TRI = nullptr;
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 265 const SIRegisterInfo *TRI, unsigned OpNo,
278 void updateByEvent(const SIInstrInfo *TII, const SIRegisterInfo *TRI,
347 const SIRegisterInfo *TRI, const MachineRegisterInfo *MRI,
370 const SIRegisterInfo *TRI = nullptr;
462 const SIRegisterInfo *TRI,
503 const SIRegisterInfo *TRI,
517 const SIRegisterInfo *TRI,
lib/Target/AMDGPU/SIInstrInfo.cpp 3180 static bool isSubRegOf(const SIRegisterInfo &TRI,
3829 const SIRegisterInfo *TRI =
4324 const SIRegisterInfo *TRI = ST.getRegisterInfo();
4407 const SIRegisterInfo *TRI = ST.getRegisterInfo();
lib/Target/AMDGPU/SIInstrInfo.h 47 const SIRegisterInfo RI;
171 const SIRegisterInfo &getRegisterInfo() const {
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 207 const SIRegisterInfo *TRI = nullptr;
lib/Target/AMDGPU/SILowerControlFlow.cpp 80 const SIRegisterInfo *TRI = nullptr;
lib/Target/AMDGPU/SILowerI1Copies.cpp 493 static bool isVRegCompatibleReg(const SIRegisterInfo &TRI,
lib/Target/AMDGPU/SILowerSGPRSpills.cpp 48 const SIRegisterInfo *TRI = nullptr;
lib/Target/AMDGPU/SIMachineFunctionInfo.cpp 189 const SIRegisterInfo &TRI) {
197 unsigned SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
204 unsigned SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
211 unsigned SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
219 unsigned SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
226 unsigned SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
233 unsigned SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) {
270 const SIRegisterInfo *TRI = ST.getRegisterInfo();
348 const SIRegisterInfo *TRI = ST.getRegisterInfo();
lib/Target/AMDGPU/SIMachineFunctionInfo.h 533 unsigned addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
534 unsigned addDispatchPtr(const SIRegisterInfo &TRI);
535 unsigned addQueuePtr(const SIRegisterInfo &TRI);
536 unsigned addKernargSegmentPtr(const SIRegisterInfo &TRI);
537 unsigned addDispatchID(const SIRegisterInfo &TRI);
538 unsigned addFlatScratchInit(const SIRegisterInfo &TRI);
539 unsigned addImplicitBufferPtr(const SIRegisterInfo &TRI);
lib/Target/AMDGPU/SIMachineScheduler.h 431 const SIRegisterInfo *SITRI;
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 272 const SIRegisterInfo *TRI = ST.getRegisterInfo();
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 37 const SIRegisterInfo *TRI;
85 static bool isEndCF(const MachineInstr &MI, const SIRegisterInfo *TRI,
192 const SIRegisterInfo *TRI = ST.getRegisterInfo();
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 73 const SIRegisterInfo *TRI;
lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp 38 const SIRegisterInfo *TRI;
lib/Target/AMDGPU/SIShrinkInstructions.cpp 229 const SIRegisterInfo &TRI = TII->getRegisterInfo();
391 const SIRegisterInfo &TRI) {
412 const SIRegisterInfo &TRI) {
418 const SIRegisterInfo &TRI) {
424 const SIRegisterInfo &TRI, const MachineRegisterInfo &MRI) {
471 const SIRegisterInfo &TRI = TII->getRegisterInfo();
lib/Target/AMDGPU/SIWholeQuadMode.cpp 150 const SIRegisterInfo *TRI;