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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10423 DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<32, AArch64::ZPRRegClassID, AArch64_AM::LSL, 16, false>());
10432 DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<32, AArch64::ZPRRegClassID, AArch64_AM::LSL, 32, false>());
10441 DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<32, AArch64::ZPRRegClassID, AArch64_AM::LSL, 64, false>());
10450 DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<32, AArch64::ZPRRegClassID, AArch64_AM::LSL, 8, false>());
10549 DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::LSL, 16, false>());
10558 DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::LSL, 32, false>());
10567 DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::LSL, 64, false>());
10576 DiagnosticPredicate DP(Operand.isSVEDataVectorRegWithShiftExtend<64, AArch64::ZPRRegClassID, AArch64_AM::LSL, 8, false>());
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc18042 AArch64_AM::getShiftType(MI.getOperand(3).getImm()) == AArch64_AM::LSL
18112 AArch64_AM::getShiftType(MI.getOperand(3).getImm()) == AArch64_AM::LSL
18121 AArch64_AM::getShiftType(MI.getOperand(3).getImm()) == AArch64_AM::LSL
18168 AArch64_AM::getShiftType(MI.getOperand(3).getImm()) == AArch64_AM::LSL
29780 AArch64_AM::getShiftType(MI.getOperand(3).getImm()) == AArch64_AM::LSL
29850 AArch64_AM::getShiftType(MI.getOperand(3).getImm()) == AArch64_AM::LSL
29859 AArch64_AM::getShiftType(MI.getOperand(3).getImm()) == AArch64_AM::LSL
29906 AArch64_AM::getShiftType(MI.getOperand(3).getImm()) == AArch64_AM::LSL
lib/Target/AArch64/AArch64ExpandImm.cpp 83 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) });
98 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) });
229 AArch64_AM::getShifterImm(AArch64_AM::LSL,
238 AArch64_AM::getShifterImm(AArch64_AM::LSL,
281 AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) });
299 AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) });
372 AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) });
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 470 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
643 AArch64_AM::getShifterImm(AArch64_AM::LSL, 0),
648 AArch64_AM::getShifterImm(AArch64_AM::LSL, 0),
lib/Target/AArch64/AArch64FastISel.cpp 735 Addr.setExtendType(AArch64_AM::LSL);
819 Addr.setExtendType(AArch64_AM::LSL);
864 Addr.setExtendType(AArch64_AM::LSL);
1078 /*TODO:IsKill=*/false, AArch64_AM::LSL,
1268 RHSIsKill, AArch64_AM::LSL, ShiftVal, SetFlags,
1282 case Instruction::Shl: ShiftType = AArch64_AM::LSL; break;
1393 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm));
1772 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftImm));
lib/Target/AArch64/AArch64FrameLowering.cpp 1032 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0))
1040 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 16))
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 317 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt);
364 return AArch64_AM::LSL;
1953 if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSL) {
2960 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
lib/Target/AArch64/AArch64InstrInfo.cpp 776 return AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL && ShiftVal <= 5;
2485 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0))
2491 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
2496 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
2550 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
2554 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
3101 AArch64_AM::getShifterImm(AArch64_AM::LSL, LocalShiftSize));
lib/Target/AArch64/AArch64InstructionSelector.cpp 4088 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt);
4444 return AArch64_AM::LSL;
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 982 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0))
lib/Target/AArch64/AArch64RegisterInfo.cpp 419 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 1155 if (isGPR64<RegClassID>() && getShiftExtendType() == AArch64_AM::LSL &&
1208 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR ||
1254 ET == AArch64_AM::LSL) &&
1273 ET == AArch64_AM::LSL) &&
1281 return (ET == AArch64_AM::LSL || ET == AArch64_AM::SXTX) &&
1302 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR ||
1313 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR ||
1324 if (ST != AArch64_AM::LSL)
1336 if (ST != AArch64_AM::LSL)
1348 return getShiftExtendType() == AArch64_AM::LSL &&
1358 return getShiftExtendType() == AArch64_AM::LSL &&
1736 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTW;
1744 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTX;
1815 AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL,
1834 AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL,
2739 .Case("lsl", AArch64_AM::LSL)
2763 if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR ||
3697 Operands.push_back(AArch64Operand::CreateShiftExtend(AArch64_AM::LSL,
lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h 55 case AArch64_AM::LSL: return "lsl";
76 case 0: return AArch64_AM::LSL;
104 case AArch64_AM::LSL: STEnc = 0; break;
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 962 if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL &&
1517 assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL &&
lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp 265 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL &&
525 assert(AArch64_AM::getShiftType(ShiftOpnd) == AArch64_AM::LSL &&