reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

  784   MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<Register> Ops);

References

include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

  333         Builder.buildMerge(MI.getOperand(DefIdx).getReg(), Regs);

lib/CodeGen/GlobalISel/CallLowering.cpp

  319           MIRBuilder.buildMerge(Args[i].OrigRegs[0], Args[i].Regs);

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

  204       MIRBuilder.buildMerge(DstReg, PartRegs);
  624       MIRBuilder.buildMerge(DstReg, DstRegs);
  679     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {SrcReg, Shift.getReg(0)});
  699     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), Srcs);
  750       MIRBuilder.buildMerge(DstReg, DstRegs);
  782     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
  934     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
 1074     MIRBuilder.buildMerge(DstReg, DstRegs);
 1258     auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD));
 1265     MIRBuilder.buildMerge(DstReg, NewMergeRegs);
 1267     auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs);
 3050     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {InL, InH});
 3123   MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {Lo.getReg(), Hi.getReg()});
 3235   MIRBuilder.buildMerge(DstReg, ResultRegs);
 3442   MIRBuilder.buildMerge(DstReg, DstRegs);
 3507     MIRBuilder.buildMerge(DstReg, DstRegs);
 3582     MIRBuilder.buildMerge(DstReg, DstRegs);

lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

  560     buildMerge(Res, Ops);

lib/Target/AArch64/AArch64CallLowering.cpp

  325                     MIRBuilder.buildMerge({NewLLT}, {CurVReg, Undef.getReg(0)})

lib/Target/AMDGPU/AMDGPUCallLowering.cpp

  496     B.buildMerge(OrigRegs[0], Regs);
  535       auto Merge = B.buildMerge(DstEltTy,

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

 1255     B.buildMerge(Dst, {Src, HighAddr.getReg(0)});
 1309   B.buildMerge(BuildPtr, {SrcAsInt, ApertureReg});
 1419   auto SignBit64 = B.buildMerge(S64, {Zero32.getReg(0), SignBit.getReg(0)});

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

  854                 B.buildMerge(LLT::scalar(64),
  909             auto Merge = B.buildMerge(OpTy, ReadlanePieces);
 1170   return B.buildMerge(LLT::vector(NumElts, S32), WideRegs).getReg(0);

lib/Target/ARM/ARMCallLowering.cpp

  392     MIRBuilder.buildMerge(Arg.Regs[0], NewRegs);

lib/Target/Mips/MipsCallLowering.cpp

  220   MIRBuilder.buildMerge(ArgsReg, VRegs);

lib/Target/X86/X86CallLowering.cpp

  358                              MIRBuilder.buildMerge(VRegs[Idx][0], Regs);
  478       MIRBuilder.buildMerge(Info.OrigRet.Regs[0], NewRegs);

unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp

  951   auto Merge0 = B.buildMerge(S24, Merge0Ops);
  960   auto Merge1 = B.buildMerge(S21, Merge1Ops);
  966   auto Merge2 = B.buildMerge(S16, Merge2Ops);
 1040   auto Merge = B.buildMerge(P0, {Lo.getReg(0), Hi.getReg(0)});

unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp

  201   auto Merge = B.buildMerge(S128, {Copies[0], Copies[1]});
  340   B.buildMerge(LLT::scalar(128), {RegC0, RegC1, RegC2, RegC3});
  344       B.buildMerge(V2x32, {RegC0, RegC1})->getOperand(0).getReg();
  346       B.buildMerge(V2x32, {RegC2, RegC3})->getOperand(0).getReg();
  348   B.buildMerge(LLT::vector(4, 32), {RegC0C1, RegC2C3});